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Progress in VLSI Design and Test

16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1-4, 2012, Proceedings

  • Conference proceedings
  • © 2012

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Editors:
  1. Hafizur Rahaman

    1. Department of Information Technology, Bengal Engineering and Science University Shibpur, Howrah, India

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  2. Sanatan Chattopadhyay

    1. Department of Electronic Science, University of Calcutta, Kolkata, India

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  3. Santanu Chattopadhyay

    1. Department of Electronics and Electrical Comm. Engg., Indian Institute of Technology Kharagpur, India

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 7373)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

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About this book

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.

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Table of contents (54 papers)

  1. Front Matter

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  3. Analog VLSI Design I

    1. Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding

      • Rahul Shrestha, Roy Paily
      Pages 30-39

    2. Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects

      • Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder
      Pages 40-45

    3. Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET

      • Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
      Pages 46-51

  4. Test and Verification I

    1. Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

      • R. Jayagowri, K. S. Gurumurthy
      Pages 52-58

    2. Post-bond Stack Testing for 3D Stacked IC

      • Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman
      Pages 59-68

    3. Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

      • Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan R. Mandal
      Pages 69-78

  5. Design Techniques I

    1. Design of High Speed Vedic Multiplier for Decimal Number System

      • Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
      Pages 79-88

    2. An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol

      • Mamata Dalui, Biplab K. Sikdar
      Pages 89-98

    3. An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs

      • Debapriya Basu Roy, Debdeep Mukhopadhyay
      Pages 99-110

  6. Algorithms and Applications I

    1. Arithmetic Algorithms for Ternary Number System

      • Subrata Das, Partha Sarathi Dasgupta, Samar Sensarma
      Pages 111-120

    2. SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output

      • Dushyant Juneja, Sougata Kar, Procheta Chatterjee, Siddhartha Sen
      Pages 121-128

    3. Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting

      • Goutam Rana, Samir Kumar Lahiri, Chirasree Roy Chaudhuri
      Pages 129-138

  7. Lower Power II

    1. Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin

      • Chandrabhan Kushwah, Santosh K. Vishvakarma
      Pages 139-146

    2. Workload Driven Power Domain Partitioning

      • Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan R. Mandal
      Pages 147-155

    3. Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit

      • Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar
      Pages 156-165

  8. Analog VLSI Design II

    1. A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL

      • Manas Kumar Hati, Tarun Kanti Bhattacharyya
      Pages 166-171
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Editors and Affiliations

  • Department of Information Technology, Bengal Engineering and Science University Shibpur, Howrah, India

    Hafizur Rahaman

  • Department of Electronic Science, University of Calcutta, Kolkata, India

    Sanatan Chattopadhyay

  • Department of Electronics and Electrical Comm. Engg., Indian Institute of Technology Kharagpur, India

    Santanu Chattopadhyay

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