Abstract
This paper presents a modified UTB SOI TFET structure and a thorough simulation study of various device design parameters on this structure.
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References
Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Letters 28(8) (August 2007)
Gandhi, R., Chen, Z., Singh, N., Banerjee, K.: Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature. IEEE Electron Device Letters 32(4) (April 2011)
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© 2012 Springer-Verlag Berlin Heidelberg
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Gupta, P.S., Kanungo, S., Rahaman, H., Dasgupta, P.S. (2012). Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_51
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DOI: https://doi.org/10.1007/978-3-642-31494-0_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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