Abstract
In this paper, a reconfigurable Residue Number System (RNS) FIR filter using higher radix multiplier is proposed. The FIR filter is implemented in direct form. The binary input is converted to Residue Number System; the resultant is processed in FIR sub-filters implemented using radix-16 multiplier and finally the result is obtained in binary form. The reconfigurable structure is designed by selecting the number of taps. Thus the proposed design provides flexibility due to reconfiguration where the number of taps is varied and the design is tested for 4,8,12 and 16 taps. Low power and high speed is achieved by Residue Number System and higher radix-16 multiplier. The proposed architecture has been implemented and synthesized using Altera DE2 Cyclone II EP2C35F672C6.
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References
Chang, C.-H.: Radix-8 Booth Encoded Modulo Multipliers with Adaptive Delay for High Dynamic Range Residue Number System. IEEE Transactions On Circuits And Systems—I: Regular Papers (2010)
Wang, Y.: Residue to binary converters based on new Chinese remainder theorems. IEEE Transactions on Circuits and Systems II, 197–206 (March 2000)
Chen, S., Wei, S.: Performance Evaluation of Signed-Digit Architecture for Weighted-To-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n -1, 2n, 2n+ 1). IPSJ Digital Courier 2 (June 2006)
Liu, Q., Wang, R.: High-speed Parallel 32×32-b Multiplier Design Using Radix-16 Booth Encoders. Computer Engineering 31(6), 200–202 (2005)
Piestrack, S.J.: Design of high speed Residue-to-binary number system converter based on chinesh Remainter Theorem. IEEE (1994)
Anderson, D.V., Özalevli, E.: A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering. IEEE Transactions On Circuits And Systems—I: Regular Papers 55(2) (March 2008)
Lindahl, A., Bengtsson, L.: Low-Power FIR filter using combined residue and radix-2 signed digit representation. In: DSD 2005 (May 2005)
Kuan-Hung, Tzi-Dar, ’.: A low power digit based Reconfigurable FIR Filter. IEEE Transactions on Circuits and Systems 53 (August 2006)
Mahesh, R., Vinod, A.P.: New Reconfigurable Architectures for implementing FIR Filter with low complexity. IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems 29 (February 2010)
Booth, A.D.: A Signed Binary Multiplication Technique. Quarterly J. Mechanics and Applied Mathematics 4(2), 236 (1951)
Woods, R.F., McQuillan, S.E., Dowling, J., McCanny, J.V.: High performance DSP ASIC for multiply, divide and square root. In: Fifth Annual IEEE International ASIC Conference and Exhibit, September 21-25, p. 2009 (1992)
Yeh, W.-C., Jen, C.-W.: High-Speed Booth Encoded Parallel Multiplier Design. IEEE Transactions on Computers 49(7), 692 (2000)
Crookes, D., Jiang, M.: Using signed digit arithmetic for low power multiplication. Electronics Letters 43(11), 613–614 (2007)
Al-Twaijry, H.A., Flynn, M.J.: Technology Scaling Effects on Multipliers. IEEE Transactions on Computers 47(11), 1201 (1998)
Jenkins, W.J.: Techniques for residue-to-analog conversion for residue encoded digital filters. IEEE Trans. Circuits Syst. CAS-25, 555–562 (1978)
Wang, Y., Song, X., Aboulhamid, M., Shen, H.: Adder Based Residue to Binary Number Converters for (2n-1, 2n, 2n+1). IEEE Transactions on Signal Processing 50(7) (July 2002)
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Britto Pari, J., Joy Vasantha Rani, S.P. (2013). Reconfigurable RNS FIR Filter Using Higher Radix Multiplier. In: Meghanathan, N., Nagamalai, D., Chaki, N. (eds) Advances in Computing and Information Technology. Advances in Intelligent Systems and Computing, vol 178. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31600-5_55
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DOI: https://doi.org/10.1007/978-3-642-31600-5_55
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