Abstract
Current steering Digital to Analog Converter (DAC) has advantage of high conversion rate and constant output impedance. A digital random return to zero technique to improve dynamic performance is presented in this paper. To demonstrate the proposed technique, 8 bit CMOS DAC is designed and layout is prepared in 90 nm technology. Computation of Integral Non Linearity (INL) and Differential Non Linearity (DNL) performance parameter is done. Chip consumes 57 mW power and 5483 (μm)2 area.
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Mathurkar, P.K., Mali, M.B. (2013). CMOS 8-Bit Current-Steering Digital Random Return to Zero DAC. In: Meghanathan, N., Nagamalai, D., Chaki, N. (eds) Advances in Computing and Information Technology. Advances in Intelligent Systems and Computing, vol 178. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31600-5_60
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DOI: https://doi.org/10.1007/978-3-642-31600-5_60
Publisher Name: Springer, Berlin, Heidelberg
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