Abstract
Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design and nanotechnology based systems. In this paper, we propose an efficient design of a reversible full adder and a reversible full subtractor. In this work, the proposed reversible full adder and reversible full subtractor is better than the existing counterparts in terms of number of reversible gates, and critical path delay. In our design, the full adders are realized using synthesizable, less transistor count and low garbage output PRT-2 gates and the full subtractor is realized using less critical path delay PRT-1 gates. VHDL is used to implement a technology-independent design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Landauer, R.: Irreversibility and heat generation in the computational process. IBM Journal of Research and Development 5, 183–191 (1961)
Bennett, C.H.: Logical reversibility of computation. IBM Journal of. Research and Development 17, 525–532 (1973)
Peres, A.: Reversible logic and quantum computers. Physical Review A 32, 3266–3276 (1985)
Perkowski, M., Al-Rabadi, A., Kerntopf, P., Buller, A., Chrzanowska-Jeske, M., Mishchenko, A., Azad Khan, M., Coppola, A., Yanushkevich, S., Shmerko, V., Jozwiak, L.: A general decomposition for reversible logic. In: Proc. RM 2001, pp. 119–138 (2001)
Perkowski, M., Kerntopf, P.: Reversible Logic. In: Proc. EURO-MICRO, Warsaw, Poland (2001)
Thapliyal, H., Srinivas, M.B.: A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. In: Srikanthan, T., Xue, J., Chang, C.-H. (eds.) ACSAC 2005. LNCS, vol. 3740, pp. 805–817. Springer, Heidelberg (2005)
Benett, C.H.: Notes on the history of reversible computation. IBM Journal of Research and Development 32, 16–23 (1998)
Haghparast, M., Navi, K.: Design of a novel fault tolerant reversible full adder for nanotechnology based systems. World Applied Sciences Journal 4, 114–118 (2008)
Hasan, H.B., Islam, R., Chowdhury, A.R., Chowdhury, S.M.A.: Reversible logic synthesis for minimization of full adder circuit. In: Euro. Micro Symposium on Digital System Design, Belek Antalya, Turkey, pp. 50–54 (2003)
Perkowski, M., Jozwiak, L., Kerntopf, P., Misohchenko, A., Al-Rabadi, A., et al.: A general decomposition for reversible logic. In: 5th Intl. RedMullar Workshop, pp. 119–138 (2001)
Azad Khan, M.H.: Design of full adder with reversible gates. In: 5th ICCIT, pp. 515–519. East West University (2002)
Haghparasat, M., Navi, K.: A Novel Reversible full adder circuit for Nanotechnology based systems. Journal of Applied Sciences 7, 3995–4000 (2007)
Hasan Babu, H., Chowdhury, A.R.: Design of a compact reversible binary coded decimal adder circuit. Journal of Systems Architecture 52, 272–282 (2006)
Haghparast, M., Jassbi, S.J., Navi, K., Hashemipour, O.: Design of a Novel Reversible Multiplier Circuit using HNG Gate in Nanotechnology. World Applied Science Journal 3, 974–978 (2008)
Rashmi, S.B., Sreedhar, H.K.: Design of a novel optimized reversible multiplier. Journal of Computing 3, 82–86 (2011)
Rashmi, S.B., Tilak, B.G., Praveen, B.: Transistor Implementation of Reversible PRT Gates International. Journal of Engineering Science and Technology 3, 2289–2297 (2011)
Murali, K.V.R.M., Sinha, N., Mahesh, T.S., Levitt, M.H., Ramanathan, K.V., Kumar, A.: Quantum information processing by Nuclear magnetic resonance:experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system. Physical Review AÂ 66, 022313 (2002)
Thapliyal, H., Ranganathan, N.: A new design of the reversible subtractor circuit. In: Proceedings of 11th IEEE International Conference on NanoTechnology, pp. 1430–1435 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
AnanthaLakshmi, A.V., Sudha, G.F. (2013). Design of a Novel Reversible Full Adder and Reversible Full Subtractor. In: Meghanathan, N., Nagamalai, D., Chaki, N. (eds) Advances in Computing and Information Technology. Advances in Intelligent Systems and Computing, vol 178. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31600-5_61
Download citation
DOI: https://doi.org/10.1007/978-3-642-31600-5_61
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31599-2
Online ISBN: 978-3-642-31600-5
eBook Packages: EngineeringEngineering (R0)