Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing

Abstract

With continuous scaling of integrated circuits into deep sub micron process technology, operating at gigahertz frequencies, it has become critical to determine system performance and reliability in interconnects. Scaling of process technology contributes to the greater proximity of adjacent interconnect wires, which leads to an increase in the amount of coupling capacitance between interconnect wires. Also, scaling in device dimensions have not scaled interconnect delays in proportion to gate delays. Thus, interconnect delays account for a major portion of circuit delay. In this paper simultaneous buffer insertion/sizing, wire sizing is done using closed form solution along with designing of Schmitt trigger as a buffer with an operating frequencies of 12-20 GHz so as to minimize crosstalk noise and delay in interconnects. Simulation results using SPICE shows that at 90nm technology node crosstalk noise is reduced by 60% and delay by 56% for 1V power supply.