Abstract
In this article, we present some architectures to carry out the convolution computation based on carry–save adders and circular buffers implemented on FPGAs. Carry-save adders are not frequent in the implementation in FPGA devices, since these have a fast carry propagation path. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry–save additions as well as carry–propagate additions using the same hardware. On the other hand, this structure of circular buffers allows the convolution computation of two signals with two algorithms of calculation: the input side algorithm and the output side algorithm, in a more efficient way.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Beuchat, J.L., Muller, J.M.: Automatic generation of modular multipliers for FPGA applications. IEEE Transactions on Computers 57(12), 1600–1613 (2008)
Ortiz, M.A., Quiles, F.J., Hormigo, J., Jaime, F.J., Villalba, J., Zapata, E.L.: Efficient implementation of carry–save adders in FPGAs. In: 20th IEEE International Conference on Application-specific System, Architectures and Processors, ASAP 2009, pp. 207–210 (2009)
Ercegovac, M.D., Lang, T.: Digital Arithmetic. Morgan Kaufmann Publishers (2004)
Steven, W.S.: Digital Signal Processing, a Practical Guide for Engineers and Scientists. Elsevier Science (2003)
Xilinx, Spartan-3 FPGA Data Sheet, http://www.xilinx.com/support/documentation/spartan-3.htm
Moreno, C.D., Quiles, F.J., Ortiz, M.A., Brox, M., Hormigo, J., Villalba, J., Zapata, E.L.: Efficient Mapping on FPGA of Convolution Computation based on Combined CSA-CPA Accumulator. In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, pp. 419–422 (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Moreno, C.D., Martínez, P., Bellido, F.J., Hormigo, J., Ortiz, M.A., Quiles, F.J. (2012). Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. In: Liñán Reyes, M., Flores Arias, J.M., González de la Rosa, J.J., Langer, J., Bellido Outeiriño, F.J., Moreno-Munñoz, A. (eds) IT Revolutions. IT Revolutions 2011. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 82. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32304-1_20
Download citation
DOI: https://doi.org/10.1007/978-3-642-32304-1_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32303-4
Online ISBN: 978-3-642-32304-1
eBook Packages: Computer ScienceComputer Science (R0)