An Efficient Management Technique for Fast SRAM Subsystems

Abstract

Today’s primitive battery technology make the energy consumption as a limiting factor to develop an embedded system. In embedded systems, memory system is the major component consuming energy since it occupies the largest area on a chip. Thus, memory system optimization is becoming more important for efficient system design and utilization. For that reason, energy efficient Scratch Pad Memories (SPMs) are thus becoming common, though unlike caches they require software management techniques.

Many embedded data-intensive applications like communication and encryption codes (viterbi, reed-solomon, etc.) usually include irregular data access patterns. Such access patterns are not amenable to a compiler with static analysis. Thus, they prevent efficient use of a SPM hierarchy for energy and performance efficiency. In this work, we present a profiling based technique. It uses memory access traces to identify data elements that can profitably be placed in the SPMs to maximize performance and energy gains.