Abstract
NAND flash memory does not support the over-write operation and NAND-based storages need to deploy flash translation layer (FTL) that emulates the standard block device interface. The main function of FTL is to perform the out-of-place update and to maintain the mapping information between the logical sector numbers and their physical locations. The aim of the work is to present the efficient FTL sector mapping scheme for resource harsh embedded systems. The prime idea is to induce the low-cost sequential merge by allocating the dedicated write buffer for the sequential block. The random blocks share the write buffer to utilize the buffer space as possible. The sequentiality of blocks is evaluated with the past write pattern. The trace-driven simulation shows that the proposed scheme improves the overall performance of NAND-based storage up to 18.6 % compared to the FTL scheme that does not induce the sequential merge.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ban, A.: Flash file system. United States Patent, No. 5,404,485 (1995)
Ban, A.: Flash file system optimized for page-mode flash technologies. United States Patent, No. 5,937,425 (1999)
Kim, J., Kim, J.M., Noh, S., Min, S., Cho, Y.: A space-efficient flash translation layer for compactflash systems. IEEE Transactions on Consumer Electronics 48, 366–375 (2002)
Lee, S., Park, D., Chung, T., Choi, W., Lee, D., Park, S., Song, H.: A log buffer based flash translation layer using fully associative sector translation. ACM Transactions on Embedded Computing Systems 6(3) (2007)
Shin, I.: Reducing computational overhead of flash translation layer with hashed page tables. IEEE Transactions on Consumer Electronics 56, 2344–2349 (2010)
Shin, I.: Light weight sector mapping scheme for NAND-based block devices. IEEE Transactions on Consumer Electronics 56, 651–656 (2010)
Kim, H., Ahn, S.: BPLRU: A buffer management scheme for improving random writes in flash storage. In: Proceedings of USENIX FAST (2008)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Shin, I. (2012). HA-SBAST: History-Based Flash Translation Layer for NAND Flash Memory. In: Lee, G., Howard, D., Kang, J.J., Ślęzak, D. (eds) Convergence and Hybrid Information Technology. ICHIT 2012. Lecture Notes in Computer Science, vol 7425. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32645-5_93
Download citation
DOI: https://doi.org/10.1007/978-3-642-32645-5_93
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32644-8
Online ISBN: 978-3-642-32645-5
eBook Packages: Computer ScienceComputer Science (R0)