Abstract
Computer systems with discrete GPUs are expected to become the standard methodology for high-speed encryption processing, but they require large amounts of power consumption and are inapplicable to embedded devices. Therefore, we have specifically examined a new heterogeneous multicore processor with CPU–GPU integration architecture. We first implemented three 128-bit block ciphers (AES, Camellia, and SC2000) from several symmetric block ciphers in an e-government recommended ciphers list by CRYPTREC in Japan using OpenCL on AMD E-350 APU with CPU–GPU integration architecture and two traditional systems with discrete GPUs. Then we evaluated their respective power efficiencies. Result showed that performance per watt of AES-128 on the APU including 80 cores were 743.0 Mbps/W and 44.0 % increases compared with those on a system equipped with a discrete AMD Radeon HD 6770 including 800 cores. This paper is the first to describe a study to evaluate the per-watt performance of block ciphers on GPUs.
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References
Cryptography Research and Evaluation Committees, http://www.cryptrec.go.jp/english/index.html
Intel Corporation: Intel SDK for OpenCL Applications 2012 Release Notes (2012)
NVIDIA Corporation: Bringing High-End Graphics to Handheld Devices (2011)
Imagination Technologies: PowerVR SGX Series5 IP Core Family (2011)
AMD Corporation: AMD Fusion. Family of APUs: Enabling a Superior, Immersive PC Experience (2011)
Khronos Group: Open Compute Language, http://www.khronos.org/
AMD Corporation: AMD Accelerated Parallel Processing OpenCL Programming Guide Revision 2.1b (2012)
New European Schemes for Signatures, Integrity and Encryption, https://www.cosic.esat.kuleuven.be/nessie/
Daemen, J., Rijmen, V.: The Design of Rijndael: AES - The Advanced Encryption Standard. Springer, Heidelberg (2002)
Aoki, K., Ichikawa, T., Kanda, M., Matsui, M., Moriai, S., Nakajima, J., Tokita, T.: Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis. In: Stinson, D.R., Tavares, S. (eds.) SAC 2000. LNCS, vol. 2012, pp. 39–56. Springer, Heidelberg (2001)
Shimoyama, T., Yanami, H., Yokoyama, K., Takenaka, M., Itoh, K., Yajima, J., Torii, N., Tanaka, H.: The Block Cipher SC2000. In: Matsui, M. (ed.) FSE 2001. LNCS, vol. 2355, pp. 312–327. Springer, Heidelberg (2002)
Daga, M., Aji, A.M., Feng, W.C.: On the Efficacy of a Fused CPU+GPU Processor (or APU) for Parallel Computing. In: Proceedings of the 2011 Symposium on Application Accelerators in High-Performance Computing, Washington, DC, USA, pp. 141–149 (2011)
Hetherington, T.H., Rogers, T.G., Hsu, L., O’Connor, M., Aamodt, T.M.: Characterizing and Evaluating a Key-value Store Application on Heterogeneous CPU-GPU Systems. In: Balasubramonian, R., Srinivasan, V. (eds.) ISPASS, pp. 88–98. IEEE (2012)
Biagio, A.D., Barenghi, A., Agosta, G., Pelosi, G.: Design of a parallel AES for graphics hardware using the CUDA framework. In: The 23rd International Parallel and Distributed Processing Symposium, pp. 1–8 (2009)
Iwai, K., Nishikawa, N., Kurokawa, T.: Acceleration of AES encryption on CUDA GPU. International Journal of Networking and Computing 2(1), 131–145 (2012)
Nishikawa, N., Iwai, K., Kurokawa, T.: Implementation of Symmetric Block Ciphers using GPGPU. In: 7th International Conference on Information Warfare and Security, Seattle, USA, pp. 222–232 (March 2012)
Gervasi, O., Russo, D., Vella, F.: The AES Implantation Based on OpenCL for Multi/many Core Architecture. In: 2010 International Conference on Computational Science and Its Applications, pp. 129–134 (2010)
Wang, X., Li, X., Zou, M., Zhou, J.: AES finalists implementation for GPU and multi-core CPU based on OpenCL. In: Proceedings of the 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2011, pp. 38–42 (2011)
The IEEE Security in Storage Working Group: XTS block cipher-based mode (XEX-based tweaked-codebook mode with ciphertext stealing), http://siswg.net/
Ma, X., Dong, M., Zhong, L., Deng, Z.: Statistical Power Consumption Analysis and Modeling for GPU-based Computing. In: Proc of ACM SOSP Workshop on Power Aware Computing and Systems Hot Power (2009)
Nagasaka, H., Maruyama, N., Nukada, A., Endo, T., Matsuoka, S.: Statistical power modeling of GPU kernels using performance counters. In: The First International Green Computing Conference, pp. 115–122 (2010)
Zhang, Y., Hu, Y., Li, B., Peng, L.: Performance and Power Analysis of ATI GPU: A Statistical Approach. In: Proceedings of the 2011 IEEE Sixth International Conference on Networking, Architecture, and Storage, NAS 2011, pp. 149–158 (2011)
Hong, S., Kim, H.: An integrated gpu power and performance model. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA 2010, pp. 280–289. ACM, New York (2010)
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Nishikawa, N., Iwai, K., Kurokawa, T. (2012). Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7439. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33078-0_25
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DOI: https://doi.org/10.1007/978-3-642-33078-0_25
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