Abstract
This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.
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References
Balster, E.J., Fortener, B.T., Turri, W.T.: Integer Computation of Lossy JPEG2000 Compression. IEEE Transactions on Image Processing 20(8) (August 2011)
Chen, K.-F., Lian, C.-J., Chen, H.-H., Chen, L.-G.: Analysis and Architecture Design of EBCOT for JPEG-2000. In: Proc. ISCAS, vol. 2 (May 2001)
Altera Corporation. NIOS II Processor Reference Handbook (December 2010)
Altera Corporation. SOPC Builder User Guide (December 2010)
Altera Corporation. NIOS II Custom Instruction User Guide (January 2011)
Altera Corporation. NIOS II Software Developer’s Handbook (February 2011)
Dyer, M., Nooshabadi, S., Taubman, D.: Design and Analysis of System on a Chip Encoder for JPEG2000. IEEE Transactions on Circuits and Systems for Video Technology 19(2) (February 2009)
Dyer, M., Taubman, D., Nooshabadi, S.: Improved Throughput Arithmetic Coder for JPEG2000. In: Proc. International Conference on Image Processing, ICIP (October 2004)
GiDEL. ProceIV Data Book (May 2011)
ISO/IEC 1.29.15444-1. JPEG 2000 Part I Final Committee Version 1.0 (September 2004)
Kumar, N.R., Xiang, W., Wang, Y.: An FPGA-Based Fast Two-Symbol Processing Architecture for JPEG2000 Arithmetic Coding. In: Proc. IEEE ICASSP (March 2010)
Liu, L., Chen, N., Meng, H., Zhang, L., Chen, H.: A VLSI Architecture of JPEG2000 Encoder. IEEE Journal of Solid-State Circuits 39(11) (November 2004)
Liu, L., Wang, Z., Chen, N., Zhang, L.: VLSI Architecture of EBCOT Tier-2 Encoder for JPEG2000. In: IEEE Workshop on Signal Processing Systems (2005)
Santa-Cruz, D., Grosbois, R., Ebrahimi, T.: JPEG 2000 performance evaluation and assessment. Signal Processing: Image Communication 17 (2002)
Sarawadekar, K., Banerjee, S.: An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000. IEEE Transactions on Circuits and Systems for Video Technology 21 (June 2011)
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McNichols, J.M., Balster, E.J., Turri, W.F., Hill, K.L. (2012). Implementation and Analysis of JPEG2000 System on a Chip. In: Bebis, G., et al. Advances in Visual Computing. ISVC 2012. Lecture Notes in Computer Science, vol 7432. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33191-6_54
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DOI: https://doi.org/10.1007/978-3-642-33191-6_54
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33190-9
Online ISBN: 978-3-642-33191-6
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