Abstract
Ever shrinking device structures are one of the main reasons for a growing inherent unreliability of embedded system components. As a remedy, various means to increase the reliability of complex embedded systems at several levels of abstraction are available. In fact, their efficient application is a key factor for the successful design of reliable embedded systems. While analysis approaches that evaluate these techniques and their advantages and disadvantages at particular levels exist, an overall system analysis that has to work cross-level is still lacking. This paper introduces a framework for cross-level reliability analysis that enables a seamless and flexible combination of various reliability analysis techniques across different levels of abstraction. For this purpose, a proposed framework provides mechanisms for (a) the composition and decomposition of the system during analysis and (b) the connection of different levels of abstraction by adapters that convert and abstract analysis results. As a case-study, the framework extends and combines three analysis approaches from the MPSoC domain: (I) a BDD-based reliability analysis considers redundancies in the system structure, (II) an analytical behavioral model to consider computational activity, and (III) a temperature simulator for processor cores. This enables to capture thermal reliability threats at transistor level in an overall system analysis. The approach is seamlessly integrated in an automatic Electronic System Level (ESL) tool flow.
Supported in part by the German Research Foundation (DFG) as associated project TE 163/16-1 of the priority program Dependable Embedded Systems (SPP 1500).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Council, J.E.D.E.: Failure mechanisms and models for semiconductor devices. JEDEC Publication JEP122-F (2010)
Eles, P., Izosimov, V., Pop, P., Peng, Z.: Synthesis of fault-tolerant embedded systems. In: Proc. of DATE 2008, pp. 1117–1122 (2008)
Ernst, D., et al.: Razor: A low-power pipeline based on circuit-level timing speculation. In: Microarchitecture 2003, pp. 7–18 (2003)
Glaß, M., Lukasiewycz, M., Reimann, F., Haubelt, C., Teich, J.: Symbolic system level reliability analysis. In: Proc. of ICCAD 2010, pp. 185–189 (2010)
Gu, Z., Zhu, C., Shang, L., Dick, R.: Application-specific MPSoC reliability optimization. IEEE Trans. on Very Large Scale Integration Systems 16(5), 603–608 (2008)
Israr, A., Huss, S.: Specification and design considerations for reliable embedded systems. In: Proc. of DATE 2008, pp. 1111–1116 (2008)
Izosimov, V., Pop, P., Eles, P., Peng, Z.: Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems. In: Proc. of DAC 2004, pp. 550–555 (2004)
Leon, A.S., Tam, K.W., Shin, J.L., Weisner, D., Schumacher, F.: A Power-Efficient High-Throughput 32-Thread SPARC Processor. IEEE Journal of Solid-State Circuits 42(1), 7–16 (2007)
Lukasiewycz, M., Glaß, M., Reimann, F., Teich, J.: Opt4J - A Modular Framework for Meta-heuristic Optimization. In: Proc. of GECCO 2011, pp. 1723–1730 (2011)
McGregor, J., Stafford, J., Cho, I.: Measuring component reliability. In: Proceedings of 6th ICSE Workshop on Component-based Software Engineering (2003)
Reussner, R., Schmidt, H., Poernomo, I.: Reliability prediction for component-based software architectures. Systems & Software 66(3), 241–252 (2003)
Sander, B., Schnerr, J., Bringmann, O.: ESL power analysis of embedded processors for temperature and reliability estimations. In: Proc. of CODES+ISSS 2009, pp. 239–248 (2009)
Schnable, G., Comizzoli, R.: CMOS integrated circuit reliability. Microelectronics Reliability 21, 33–50 (1981)
Skadron, K., Stan, M., Huang, W., Velusamy, S., Sankaranarayanan, K., Tarjan, D.: Temperature-aware microarchitecture. In: ACM SIGARCH Computer Architecture News, vol. 31, pp. 2–13 (2003)
Stathis, J.: Reliability limits for the gate insulator in CMOS technology. IBM Journal of Research and Development 46(2-3), 265–286 (2002)
Streichert, T., Glaß, M., Haubelt, C., Teich, J.: Design space exploration of reliable networked embedded systems. J. on Systems Architecture 53(10), 751–763 (2007)
Ting, L., May, J., Hunter, W., McPherson, J.: AC electromigration characterization and modeling of multilayeredinterconnects. In: 31st Annual International Reliability Physics Symposium, pp. 311–316 (1993)
Tosun, S., Mansouri, N., Arvas, E., Kandemir, M., Xie, Y.: Reliability-centric high-level synthesis. In: Proc. of DATE 2005, pp. 1258–1263 (2005)
Wandeler, E., Thiele, L.: Real-Time Calculus (RTC) Toolbox, http://www.mpa.ethz.ch/Rtctoolbox
Wei, B., Vajtai, R., Ajayan, P.: Reliability and current carrying capacity of carbon nanotubes. Applied Physics Letters 79, 1172–1174 (2001)
Wirthlin, M., Johnson, E., Rollins, N., Caffrey, M., Graham, P.: The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets. In: Proc. of FCCM 2003, pp. 133–142 (2003)
Xiang, Y., Chantem, T., Dick, R.P., Hu, X.S., Shang, L.: System-Level Reliability Modeling for MPSoCs. In: Proc. of CODES+ISSS 2010, pp. 297–306 (2010)
Xie, Y., Li, L., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: Reliability-aware co-synthesis for embedded systems. VLSI Signal Processing 49(1), 87–99 (2007)
Zhang, Y., Dick, R., Chakrabarty, K.: Energy-aware deterministic fault tolerance in distributed real-time embedded systems. In: Proc. of DATE 2005, pp. 372–377 (2005)
Zhu, C., Gu, Z., Dick, R., Shang, L.: Reliable multiprocessor system-on-chip synthesis. In: Proc. of CODES+ISSS 2007, pp. 239–244 (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Glaß, M., Yu, H., Reimann, F., Teich, J. (2012). Cross-Level Compositional Reliability Analysis for Embedded Systems. In: Ortmeier, F., Daniel, P. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2012. Lecture Notes in Computer Science, vol 7612. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33678-2_10
Download citation
DOI: https://doi.org/10.1007/978-3-642-33678-2_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33677-5
Online ISBN: 978-3-642-33678-2
eBook Packages: Computer ScienceComputer Science (R0)