Abstract
We present a proof of correctness in Matita for an optimising assembler for the MCS-51 microcontroller. The efficient expansion of pseudoinstructions, namely jumps, into machine instructions is complex. We isolate the decision making over how jumps should be expanded from the expansion process itself as much as possible using ‘policies’, making the proof of correctness for the assembler more straightforward.
Our proof strategy contains a tracking facility for ‘good addresses’ and only programs that use good addresses have their semantics preserved under assembly, as we observe that it is impossible for an assembler to preserve the semantics of every assembly program. Our strategy offers increased flexibility over the traditional approach to proving the correctness of assemblers, wherein addresses in assembly are kept opaque and immutable. In particular, we may experiment with allowing the benign manipulation of addresses.
The project CerCo acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the Seventh Framework Programme for Research of the European Commission, under FET-Open grant number: 243881.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Asperti, A., Sacerdoti Coen, C., Tassi, E., Zacchiroli, S.: User interaction with the Matita proof assistant. Automated Reasoning 39, 109–139 (2007)
Boender, J., Sacerdoti Coen, C.: On the correctness of a branch displacement algorithm (2012), http://arxiv.org/abs/1209.5920
The CerCo FET-Open project (2011), http://cerco.cs.unibo.it/
Branch displacement optimisation (2006), http://groups.google.com/group/alt.lang.asm/msg/d31192d442accad3
Klein, G., Andronick, J., Elphinstone, K., Heiser, G., Cock, D., Derrin, P., Elkaduwe, D., Engelhardt, K., Kolanski, R., Norrish, M., Sewell, T., Tuch, H., Winwood, S.: seL4: Formal verification of an operating system kernel. In: SOSP (2009)
Klein, G., Nipkow, T.: A machine-checked model for a Java-like language, virtual machine and compiler. ACM Transactions on Programming Languages and Systems 28(4), 619–695 (2006)
Leroy, X.: A formally verified compiler back-end. Automated Reasoning 43(4), 363–446 (2009)
Moore, J.S.: Piton: A mechanically verified assembly language. Automated Reasoning Series, vol. 3. Springer (1996)
Moore, J.S.: A grand challenge proposal for formal methods (2005)
Small device C compiler 3.0.0 (2011), http://sdcc.sourceforge.net/
Siemens Semiconductor Group 8051 derivative instruction set (2011), http://www.win.tue.nl/~aeb/comp/8051/instruction-set.pdf
Sozeau, M.: Subset Coercions in Coq. In: Altenkirch, T., McBride, C. (eds.) TYPES 2006. LNCS, vol. 4502, pp. 237–252. Springer, Heidelberg (2007)
Tuch, H., Klein, G., Norrish, M.: Types, bytes, and separation logic. In: POPL, pp. 97–108 (2007)
Ševčík, J., Vafeiadis, V., Zappa Nardelli, F., Jagannathan, S., Sewell, P.: Relaxed-memory concurrency and verified compilation. In: POPL, pp. 43–54 (2011)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mulligan, D.P., Sacerdoti Coen, C. (2012). On the Correctness of an Optimising Assembler for the Intel MCS-51 Microprocessor. In: Hawblitzel, C., Miller, D. (eds) Certified Programs and Proofs. CPP 2012. Lecture Notes in Computer Science, vol 7679. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35308-6_7
Download citation
DOI: https://doi.org/10.1007/978-3-642-35308-6_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-35307-9
Online ISBN: 978-3-642-35308-6
eBook Packages: Computer ScienceComputer Science (R0)