Abstract
Accurate timing analysis of digital integrated circuits is becoming harder to achieve with current and future CMOS technologies. The shrinking feature sizes lead to increasingly important local process variations (PV), making existing methods like corner-based static timing analysis (STA) yield overly pessimistic results. In this paper we propose a general purpose statistical circuit simulator for accurate timing analysis. A statistical simplified transistor model (SSTM) is used as the simulator’s building block, allowing accurate simulation of sequential circuits while fast statistical analysis is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45nm CMOS technology.
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References
Hitchcock, R.B., Smith, G.L., Cheng, D.D.: Timing Analysis of Computer Hardware. IBM Journal of Research and Development, 100–105 (1982)
Hitchcock, R.B.: Timing Verification and the Timing Analysis program. In: Proc. of the DAC, pp. 594–604 (1982)
Blaauw, D., Chopra, K., Srivastava, A., Scheffer, L.: Statistical Timing Analysis: From Basic Principles to State the Art. IEEE Trans. on CAD of Integrated Circuits and Systems, 589–607 (2008)
Berkelaar, M.: Statistical Delay Calculation, a Linear Time Method. In: Proc. of TAU, pp. 15–24 (1997)
Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S.G., Narayan, S.: First-Order Incremental Block-Based Statistical Timing Analysis. In: Proc. of the DAC, pp. 331–336 (2004)
Agarwal, A., Blaauw, D., Zolotov, V.: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. In: Proc. of the IEEE/ACM ICCAD, pp. 900–907 (2003)
Croix, J.F., Wong, D.F.: Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models. In: Proc. of the DAC, pp. 386–389 (2003)
Nazarian, S., Fatemi, H., Pedram, M.: Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling. IEEE Trans. Very Large Scale Integrated Systems, 92–103 (2011)
Fatemi, H., Nazarian, S., Pedram, M.: Statistical Logic Cell Delay Analysis Using a Current-based Model. In: Proc. of the DAC, pp. 253–256 (2006)
Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems, 1114–1125 (2007)
Oh, N., Ding, L., Kasnavi, A.: Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop. In: Proc. of the ISQED, pp. 153–159 (2006)
Amin, C., Kashyap, C., Menezes, N., Killpack, K., Chiprout, E.: A Multi-port Current Source Model for Multiple-Input Switching Effects in CMOS Library Cells. In: Proc. of the DAC, pp. 247–252 (2006)
Tang, Q., Zjajo, A., Berkelaar, M., van der Meijs, N.: RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis. In: Proc. of the DAC, pp. 787–792 (2010)
Tang, Q., Zjajo, A., Berkelaar, M., van der Meijs, N.: Transistor-level gate model based statistical timing analysis considering correlations. In: DATE, pp. 917–922 (2012)
UC Berkeley. BSIM4 MOSFET Model (2003), http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4
Nangate 45nm Open Cell Library (2009), http://www.nangate.com/?page_id=22
Ho, C.W., Ruehli, A., Brennan, P.: The Modified Nodal Approach to Network Analysis. IEEE Transactions on Circuits and Systems, 504–509 (1975)
Najm, F.N.: Circuit Simulation. Wiley-IEEE Press (2010)
Soong, T.T.: Random Differential Equations in Science and Engineering. Academic Press, New York (1973)
Tang, Q.: Personal communication
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RodrÃguez, J., Tang, Q., Zjajo, A., Berkelaar, M., van der Meijs, N. (2013). Direct Statistical Simulation of Timing Properties in Sequential Circuits. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_14
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DOI: https://doi.org/10.1007/978-3-642-36157-9_14
Publisher Name: Springer, Berlin, Heidelberg
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