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Low-Power Delay Sensors on FPGAs

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2012)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7606))

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Abstract

This paper investigates design and implementation issues of all-digital delay sensors implemented on FPGAs. The delay sensors discussed here are suitable for monitoring of digital systems during operation. Two topology families are studied. Focusing on power reduction in addition to quality of measurement, corresponding power dissipation reduction techniques are introduced, fully characterized by measurements on actual FPGA hardware implementations. The proposed delay sensors derived by means of an introduced design method, reduce power consumption by 31% for cases of practical interest.

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Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, University of Patras, Greece

    Panagiotis Sakellariou & Vassilis Paliouras

Authors
  1. Panagiotis Sakellariou
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  2. Vassilis Paliouras
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Editor information

Editors and Affiliations

  1. Facultad de Informática, Complutense University of Madrid, 28040, Madrid, Spain

    José L. Ayala

  2. School of Electronic Engineering, Newcastle University, NE1 7RU, Newcastle upon Tyne, England, UK

    Delong Shang  & Alex Yakovlev  & 

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Sakellariou, P., Paliouras, V. (2013). Low-Power Delay Sensors on FPGAs. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_20

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  • DOI: https://doi.org/10.1007/978-3-642-36157-9_20

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36156-2

  • Online ISBN: 978-3-642-36157-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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