Abstract
Our contribution lies in offering a fast and parametrized domain-space exploration to the designer, whose expertise drives the whole process while staying the actor of added-value creation. In this paper, we present two new features and two important improvements of our H-MPSoC synthesis framework. The first one is a new template-based approach for automated design space exploration and synthesis. A template describes an architecture model for a specific domain and has three levels of specifications each representing a different level of design expertise. We also rely on the Model-Driven Architecture (MDA) paradigm to provide flexibility, reusability and code generation for different FPGA targets. We have refined the communication models to get more accurate performance estimations. Finally, we also improved our mapping decision algorithm that drastically reduces the simulation time. The output is the synthesizable code of the hardware architecture, the adapted C code of the application and the project files for FPGA design tools. We use an MJPEG decoder as a case-study to validate our framework on a Xilinx FPGA.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Oliveira, M., Brião, E., Francisco, A., Wagner, R.: Model driven engineering for MPSOC design space exploration. In: Proc. of the 20th Annual Conf. on Integrated Circuits and Systems Design, SBCCI 2007, pp. 81–86. ACM (2007)
Atitallah, R., Piel, E., Niar, S., Marquet, P., Dekeyser, J.: Multilevel MPSoC simulation using an MDE approach. In: IEEE Intl. SOC Conf. (2007)
Thompson, M., et al.: A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. In: 5th Conference on Hardware/Software Codesign and System Synthesis (2007)
Kahn, G.: The semantics of a simple language for parallel programming. Information processing 74, 471–475 (1974)
Coussy, P., et al.: GAUT: A High-Level Synthesis Tool for DSP applications. Springer (2008)
Nikolov, H., et al.: Systematic and automated multiprocessor system design, programming, and implementation. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 27(3), 542–555 (2008)
Verdoolaege, S., Nikolov, H., Stefanov, T.: Pn: a tool for improved derivation of process networks. EURASIP Journal on Embedded Systems 2007(1), 19 (2007)
Xilinx, OS and Libraries Document Collection (UG 643), http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/oslib_rm.pdf
Corre, Y., et al.: A framework for high-level synthesis of heterogeneous mp-soc. In: Proc. of the Great Lakes Symp. on VLSI, pp. 283–286. ACM (2012)
Benkrid, K., Akoglu, A., Ling, C., Song, Y., Liu, Y., Tian, X.: High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP. International Journal of Reconfigurable Computing (2012)
Feiler, P.H.: The architecture analysis & design language (aadl): An introduction. Technical report, DTIC Document (2006)
Kuhn, H.W.: The hungarian method for the assignment problem. Naval Research Logistics Quarterly 2(1-2), 83–97 (1955)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Corre, Y., Diguet, JP., Lagadec, L., Heller, D., Blouin, D. (2013). Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA. In: Brisk, P., de Figueiredo Coutinho, J.G., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2013. Lecture Notes in Computer Science, vol 7806. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36812-7_15
Download citation
DOI: https://doi.org/10.1007/978-3-642-36812-7_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36811-0
Online ISBN: 978-3-642-36812-7
eBook Packages: Computer ScienceComputer Science (R0)