Abstract
The Networks-on-Chip paradigm has been seen as an interconnect architecture solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip. Moreover, the execution of different applications requires flexible and transparent interconnection solutions, and this feature is best provided by a selfadaptable system. In this paper we propose HASIN, an architecture that explores the suitable switching architecture according to the traffic in each region of the system, in a hierarchical manner. The proposed interconnection allows adapting the network at runtime using three switching possibilities to reconfigure itself according to the floorplan information. HASIN allows increasing the throughput up to 77% and reducing the power consumption up to 76% when compared to a packet-switched mesh network-on-chip.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Silvano, C., et al.: Low Power Networks-on-Chip, 1st edn., p. 300. Springer (2011)
Stensgaard, M., Sparso, J.: ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. In: NoCS, pp. 55–64 (2008)
Das, R., Eachempati, S., et al.: Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs. In: HPCA, pp. 175–186 (2009)
Modarressi, M., et al.: Virtual Point-to-Point Connections for NoCs. TCAD 29(6), 855–868 (2010)
Jerger, N., et al.: Circuit-Switched Coherence. In: NoCS, pp. 193–202 (2008)
Modarressi, M., et al.: A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM. In: DATE, pp. 566–569 (2009)
Yoon, Y., et al.: Virtual Channels vs. Multiple Physical Networks: a Comparative Analysis. In: DAC, pp. 162–165 (2010)
Chou, S.-H., et al.: Hierarchical Circuit-Switched NoC for Multicore Video Proc-essing. In: Microprocess. Microsyst. (2010)
Murali, S., et al.: Synthesis of networks on chips for 3D systems on chips. In: ASP-DAC, pp. 242–247 (2009)
Tino, A., Khan, G.: Power and Performance Tabu Search Based Multicore Network-on-Chip Design. In: Intl.Conf. on Parallel Processing, pp. 74–81 (2010)
Matos, D., et al.: Floorplanning-Aware Design Space Exploration for Applica-tion-Specific Hierarchical Network-on-Chip. In: NoCARC (2011)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Matos, D., Reinbrecht, C., Kreutz, M., Palermo, G., Carro, L., Susin, A. (2013). Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability. In: Brisk, P., de Figueiredo Coutinho, J.G., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2013. Lecture Notes in Computer Science, vol 7806. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36812-7_17
Download citation
DOI: https://doi.org/10.1007/978-3-642-36812-7_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36811-0
Online ISBN: 978-3-642-36812-7
eBook Packages: Computer ScienceComputer Science (R0)