Design of Low Power FSM Using Verilog in VLSI

Abstract

With day by day increase in integration density of CMOS technology the concern for area usage for VLSI circuits is increased,giving more importance to timing and power dissipation constraints. Controllers are running continuosly so critical for power (while parts of the data path may be shut down), and for timing because the delay through the controller may constrain the delay through the data path.

In this work we propose a procedure for the decomposition of a network of interacting FSMs starting from a single state-table specification. The straightforward singlemachine implementation is called undecomposed FSM. We call decomposed FSM the interacting FSM implementation. The sub-machines in the decomposed FSM communicate through a set of l interface signals. The decomposed implementation has low power dissipation because one single sub-machine is clocked at any given time and it controls the outputs values while all other sub-machines are idle: they do not receive the clock signal and dissipate little power. When a sub-machine terminates its execution, it sends an activation signal to another sub-machine which takes control of the computation, then it de-activates itself.