Abstract
Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energy-efficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irreversible bit erasures occurring in a combinatorial implementation, showing considerable potential for minimizing the logical information loss.
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Hänninen, I., Lu, H., Lent, C.S., Snider, G.L. (2013). Energy Recovery and Logical Reversibility in Adiabatic CMOS Multiplier. In: Dueck, G.W., Miller, D.M. (eds) Reversible Computation. RC 2013. Lecture Notes in Computer Science, vol 7948. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-38986-3_3
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DOI: https://doi.org/10.1007/978-3-642-38986-3_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-38985-6
Online ISBN: 978-3-642-38986-3
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