Abstract
In this paper we propose a combination of capabilities of the FPGA based device and PC computer for data processing using rough set methods. Presented architecture has been tested on a random data. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough sets operations in comparison to software implementation.
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Grześ, T., Kopczyński, M., Stepaniuk, J. (2013). FPGA in Rough Set Based Core and Reduct Computation. In: Lingras, P., Wolski, M., Cornelis, C., Mitra, S., Wasilewski, P. (eds) Rough Sets and Knowledge Technology. RSKT 2013. Lecture Notes in Computer Science(), vol 8171. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41299-8_25
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DOI: https://doi.org/10.1007/978-3-642-41299-8_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-41298-1
Online ISBN: 978-3-642-41299-8
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