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A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

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Computer Engineering and Technology (NCCET 2013)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 396))

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Abstract

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

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Chen, X., Xing, Z., Sui, B. (2013). A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds) Computer Engineering and Technology. NCCET 2013. Communications in Computer and Information Science, vol 396. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41635-4_26

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  • DOI: https://doi.org/10.1007/978-3-642-41635-4_26

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-41634-7

  • Online ISBN: 978-3-642-41635-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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