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A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

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Computer Engineering and Technology (NCCET 2013)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 396))

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Abstract

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

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References

  1. Likharev, K.K.: Single-Electron Devices and Their Applications. Proceedings of the IEEE 87(4), 606–632 (1999)

    Google Scholar 

  2. Wang, W., Liu, M., Hsu, A.: Hybrid nanoelectronics: Future of computer technology. J. Comput. Sci. Technol. 21(6), 871–886 (2006)

    Article  Google Scholar 

  3. Ionescu, A.M., Declercq, M.J., Mahapatra, S., Banerjee, K., Gautier, J.: Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits. In: Proceedings of 39th Design Automation Conference, pp. 323–328 (June 2002)

    Google Scholar 

  4. Mahapatra, S., Ionescu, A.M.: Hybrid CMOS Single Electron Transistor Device and Circuit Design. Artech House Publication (2006)

    Google Scholar 

  5. Venkataratnam, A., Goel, A.K.: Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature. Microelectronics Journal 39, 1461–1468 (2008)

    Article  Google Scholar 

  6. Parekh, R., Beaumont, A., Beauvais, J., Drouin, D.: Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation. IEEE Trans. Electron Devices 59(4), 918–923 (2012)

    Article  Google Scholar 

  7. Uchida, K., Koga, J., Ohba, R., Toriumi, A.: Programmable singleelectron transistor logic for future low-power intelligent LSI: Proposal and room-temperature operation. IEEE Trans. Electron Devices 50(7), 1623–1630 (2003)

    Article  Google Scholar 

  8. Sui, B.C., Chi, L.F.Y.Q., Zhang, C.: Nano-Reconfigurable Cells With Hybrid Circuits of Single-Electron Transistors and MOSFETs. IEEE Trans. on Electron Devices 57(9), 2251–2257 (2010)

    Article  Google Scholar 

  9. Inokawa, H., Fujiwara, A., Takahashi, Y.: A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. IEEE Trans. Electron Devices 50(2), 462–470 (2003)

    Article  Google Scholar 

  10. Saitoh, M., Harata, H., Hiramoto, T.: Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching. In: IEDM Tech. Dig., San Francisco, CA, pp. 187–190 (2004)

    Google Scholar 

  11. Song, K.W., Lee, Y.K., Sim, J.S., Jeoung, H., Lee, J.D., Park, B.G., Jin, Y.S., Kim, Y.W.: SET/CMOS Hybrid Process and Multiband Filtering Circuits. IEEE Trans. Electron Devices 52(8), 1845–1850 (2005)

    Article  Google Scholar 

  12. Wei, R.S., Chen, J.F., Chen, S.C., He, M.H.: Reconfigurable Threshold Logic Element with SET and MOS Transistors. Chin. Phys. Lett. 29(2), 028502 (2012)

    Google Scholar 

  13. Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-Power CMOS Digital Design. IEEE Journal of Solid State Circuits 27(4), 473–484 (1992)

    Article  Google Scholar 

  14. Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Pearson Education (2003)

    Google Scholar 

  15. Wasshuber, C., Kosina, H., Selberherr, S.: SIMON-a simulator for single-electron tunnel devices and circuits. IEEE Trans. Comput. Aided Design 16, 937–944 (1997)

    Article  Google Scholar 

  16. Zardalidis, G., Karafyllidis, I.G.: SECS: A New Single-Electron-Circuit Simulator. IEEE Trans. Circuits Syst. I, Reg. Papers 55(9), 2774–2784 (2008)

    Article  MathSciNet  Google Scholar 

  17. Inokawa, H., Takahashi, Y.: A compact analytical model for asymmetric single-electron tunneling transistors. IEEE Trans. Electron Devices 50(2), 455–461 (2003)

    Article  Google Scholar 

  18. Mahapatra, S., Vaish, V., Wasshuber, C., Banerjee, K., Ionescu, A.M.: Analytical modeling of single electron transistor for hybrid CMOSSET analog IC design. IEEE Trans. Electron Devices 51(11), 1772–1782 (2004)

    Article  Google Scholar 

  19. Zhang, F., Tang, R., Kim, Y.-B.: SET-based nano-circuit simulation and design method using HSPICE. Microelectron. J. 36(8), 741–748 (2005)

    Article  Google Scholar 

  20. Inokawa, H., Takahashi, Y.: Experimental and simulation studies of single-electron-transistor-based multiple-valued logic. In: Proc. 33rd Int. Symp. Multiple-Valued Logic, pp. 259–266 (May 2003)

    Google Scholar 

  21. Zhang, W., Wu, N.J., Hashizume, T., Kasai, S.: Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors. IEEE Trans. Nanotechnol. 6(2), 146–157 (2007)

    Article  Google Scholar 

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Authors and Affiliations

  1. Institute of Microelectronics, School of Computer, National University of Defense Technology, Changsha, Hunan, 410073, P.R. China

    Xiaobao Chen, Zuocheng Xing & Bingcai Sui

Authors
  1. Xiaobao Chen
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  2. Zuocheng Xing
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  3. Bingcai Sui
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Editor information

Editors and Affiliations

  1. National University of Defense Technology, Changsha, China

    Weixia Xu  & Liquan Xiao  & 

  2. School of Computer, National University of Defense Technology, 410073, Changsha, Hunan, P.R. China

    Chengyi Zhang

  3. National University of Defense Technology, Changsha, P.R. China

    Jinwen Li

  4. School of Computer Science, National University of Defense Technology, Changsha, Hunan, P.R. China

    Liyan Yu

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Chen, X., Xing, Z., Sui, B. (2013). A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds) Computer Engineering and Technology. NCCET 2013. Communications in Computer and Information Science, vol 396. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41635-4_26

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  • DOI: https://doi.org/10.1007/978-3-642-41635-4_26

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-41634-7

  • Online ISBN: 978-3-642-41635-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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