CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time

Abstract

With growing complexities of SoC, number of on-chip peripheral is also increasing and it is mandatory for SoC engineer to meet the I/O AC timing in Static Timing Analysis (STA). But, at times, it is found that I/O timing are failing or passing marginally, when Si is tested on Automated Testing Equipment (ATE). Failing of I/O AC specifications leads to extensive debugging of Si on ATE, resulting test time increase, yield loss & further revision of Si. This paper proposes a method whereby extra margin has been built on I/O AC timing closure of all peripherals in the design phase itself, keeping targeted Coefficient of Process Capability (CPK) in mind. It has been shown that using this approach, most of the peripherals meet ~ CPK of 2 when tested on different SoC. Consequently, ATE test time and yield loss is reduced.