Abstract
Power gating is used in almost all Low-power devices to lower leakage. In this power gating, the three important design parameters are the domain-wakeup latency (from sleep to active mode transition) time, the inrush-current when the power switches are turned on, and the voltage dip caused by the inrush current. Also, the analysis of these parameters has some uniqueness when there is an on-die power-supply system. In this paper we present a methodology for analyzing these parameters, followed by a case study involving analysis of all these parameters using circuit simulation (SPICE) for a wakeup latency critical low power SoC (System on a Chip).
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References
Shi, K., Flynn, D.: Power Gating Design Tradeoffs and Consideration in Production Low-power Designs. In: Proc. of the IEC DesignCon (February 2009)
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© 2013 Springer-Verlag Berlin Heidelberg
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Singhal, V., Dey, A., Mallala, S., Paul, S. (2013). A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_35
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DOI: https://doi.org/10.1007/978-3-642-42024-5_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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