Abstract
Design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. In this paper, it is shown that in an (n×n) reversible circuit implemented with k-CNOT gates, addition of only two extra inputs along with at most 5 k-CNOT gates per gate can yield an easily testable design. The modified design admits a universal test set of size (n + 2) that detects all SMGFs, PMGFs, and detectable RGFs in the circuit.
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Mondal, J., Das, D.K., Kole, D., Rahaman, H., Bhattacharya, B.B. (2013). On Designing Testable Reversible Circuits Using Gate Duplication. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_38
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DOI: https://doi.org/10.1007/978-3-642-42024-5_38
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