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10 Gbps Current Mode Logic I/O Buffer

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VLSI Design and Test

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 382))

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Abstract

A new architecture for a high speed CML buffer is presented. The buffer is designed for OC-192/STM-64 applications to be used in the limiting amplifier which is a critical block in optical communication systems. OC-192/STM-64 works around 10Gbps. The proposed architecture is also more efficient in terms of area.

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References

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Author information

Authors and Affiliations

  1. Dhirubhai Ambani Institue of Information and Communication Technology, Gandhinagar, India

    Akhil Rathore

  2. Institute of ICT, Ahmedabad University, Ahmedabad, India

    Chetan D Parikh

Authors
  1. Akhil Rathore
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  2. Chetan D Parikh
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Editor information

Editors and Affiliations

  1. MNIT, Jaipur, India

    Manoj Singh Gaur , Vijay Laxmi  & Dharmendra Boolchandani ,  & 

  2. University of Southampton, UK

    Mark Zwolinski

  3. IIT Bombay, Mumbai, India

    Virendra Sing

  4. Auburn University, AL, USA

    Adit D. Sing

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© 2013 Springer-Verlag Berlin Heidelberg

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Rathore, A., Parikh, C.D. (2013). 10 Gbps Current Mode Logic I/O Buffer. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_8

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  • DOI: https://doi.org/10.1007/978-3-642-42024-5_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-42023-8

  • Online ISBN: 978-3-642-42024-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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