Abstract
The paper proposes the implementation of two non-cyclic data permutations within shift register memories to provide random access to 2n-1 data in at most 2(n-1) units of time and sequential access to memory pages of 29 data (g ≤ n) in 3 (2g-1-1) units of time.
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References
H.S. Stone: ‘Dynamic Memories with Enhanced Data Access’ IEEE — TC, Vol. C-21, No. 4(1972), pp. 359–365
W.H. Kautz: ‘Shift Register Memories’, IEEE Comp. Soc. Repos. Serv. R 73–48
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© 1976 Springer-Verlag Berlin · Heidelberg
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Kluge, W. (1976). On the Problem of Fast Random and Sequential Data Access in Shift Register Memories. In: Händler, W., Bell, R.K. (eds) Computer Architecture. Informatik-Fachberichte, vol 4. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-66400-7_15
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DOI: https://doi.org/10.1007/978-3-642-66400-7_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-07761-9
Online ISBN: 978-3-642-66400-7
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