Skip to main content

Random Testing of LSI Self-Checking Circuits

  • Conference paper
Fehlertolerierende Rechensysteme

Part of the book series: Informatik-Fachberichte ((INFORMATIK,volume 84))

Abstract

The principle of random testing is to apply a sequence of random input patterns simultaneously to both a circuit under test and a reference circuit. The outputs are compared. The research aim is to determine the test length (number of input patterns to apply) to obtain a given test quality. In the case of the microprocessor one applies a sequence of random instructions with random data, and a method of evaluating an upper bound for a detecting sequence has been defined in previous works. This paper recalls the method and concerns extensions to use it for LSI circuits which are not microprocessors. One gives results (test lengths) for three LSI self-checking circuits and more general comments about random testing of self-checking circuits. Some experimental results are presented in a summary form.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M.S. ABADIR, H.K. REGHBATI “LSI Testing Techniques”, IEEE Micro, Vol. 3, n° 1, February 1983, pp. 34–51.

    Google Scholar 

  2. R. DAVID “Signature Analysis for Multi-Output Circuits”, 14th Int. Symp. Fault-Tolerant Computing, June 1984, pp. 366–371.

    Google Scholar 

  3. W. LUCIW “Can an User test LSI Microprocessors Effectively ?”, IEEE Trans. Manufacturing & Technology, Vol. MFT-5, n° 1, March 1976, pp. 21–23.

    Article  Google Scholar 

  4. R. DAVID, P. THEVENOD-FOSSE “Random Testing of Integrated Circuits”, IEEE Trans. Instrumentation and Measurement, Vol. IM-30, n° 1, March 1981, pp. 20–25.

    Google Scholar 

  5. X. FEDI, R. DAVID “Experimental Results from Random Testing of Microprocessors”, 14th Int. Symp. Fault-Tolerant Computing, June 1984, pp. 225–230.

    Google Scholar 

  6. J.J. SHEDLETSKY, E. J. MCCLUSKEY “The Error Latency of a Fault in a Sequential Digital Circuit”, IEEE Trans. Computers, Vol. C-25, n° 6, June 1976, pp. 655–659.

    MathSciNet  Google Scholar 

  7. P. THEVENOD-FOSSE, R. DAVID “Random Testing of the Data Processing Section of a Microprocessor”, 11th Int. Symp. Fault-Tolerant Computing, June 1981, pp. 275–280.

    Google Scholar 

  8. P. THEVENOD-FOSSE, R. DAVID “Random Testing of the Control Section of a Microprocessor”, 13th Int. Symp. Fault-Tolerant Computing, June 1983, pp. 366–373.

    Google Scholar 

  9. P. THEVENOD-FOSSE “Longueur de test aléatoire du microprocesseur Motorola 6800”, Journées d’Electronique 1983, EPF Lausanne, October 1983, pp. 181–191.

    Google Scholar 

  10. M. DIAZ “Design of Totally Self-Checking and Fail Safe Sequential Machines”, 4th Int. Symp. Fault-Tolerant Computing, June 1974, pp. 3. 19–3. 24.

    Google Scholar 

  11. H. DENEUX, P. THEVENOD-FOSSE, L. BEGHIN “Test aléatoire de circuits développés par le CNET/CNS”, 4th Int. Conference on Reliability and Maintainability, Perros-Guirec, May 1984, pp. 542–548.

    Google Scholar 

  12. H. DENEUX, P. THEVENOD-FOSSE, L. BEGHIN “Test aléatoire de circuits fabriqués par le CNET: étude théorique et expérimentations”, Final Report Convention CNET 83 3B 013, June 1984.

    Google Scholar 

  13. H. DENEUX “Test aléatoire de circuits fabriqués par le CNET: étude théorique et expérimentations. Cas du Codeur de Hamming Autotestable CHA”, LAG n° 84–06, Report “December 1983 - February 1984 ” Convention CNET 83 3B 013, February 1984.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1984 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Deneux, H., Thevenod-Fosse, P. (1984). Random Testing of LSI Self-Checking Circuits. In: Großpietsch, KE., Dal Cin, M. (eds) Fehlertolerierende Rechensysteme. Informatik-Fachberichte, vol 84. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-69698-5_31

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-69698-5_31

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-13348-3

  • Online ISBN: 978-3-642-69698-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics