Skip to main content

The Detection of Small Size Multiple Faults by Single Fault Test Sets in Programmable Logic Arrays

  • Conference paper
Fehlertolerierende Rechensysteme

Part of the book series: Informatik-Fachberichte ((INFORMATIK,volume 84))

  • 41 Accesses

Abstract

In this paper we present a method to quantitively predict the multiple fault coverage capability of a single fault detection test set in a PLA. The method enables to determine the coverage ratio defined as the ratio of the number of multiple contact faults detected by a single fault test Tc to the total number of all multiple faults. The analysis is divided into two parts. First we consider multiple faults which do not contain any four-way masking cycle. Next, the masking relations are studied in detail and it is shown that Tc detects significant percentage of faults with four-way masking cycle. Based on these results the bounds of coverage capability of Tc are determined. It is shown that the multiple fault coverage ratio dr increases with increasing number of rows of a PLA and the ratio drops with increasing size of faults.

Index Terms — PLA testing, contact faults, fault masking, multiple fault detection, fault coverage, worst case coverage.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. V.K. Agarwal, “Multiple fault detection in Programmable Logic Arrays”, IEEE Trans. Comput.,vol. 0–29, pp. 518–522, June 1980.

    Article  Google Scholar 

  2. V.K. Agarwal and G.M. Masson, “Generic fault characterizations for table-look-up coverage bounding”, IEEE Trans. Comput.,vol.C-29,pp. 288–299, April 1980.

    Google Scholar 

  3. V.K. Agarwal and A.S.F. Fung, “Multiple fault testing of large circuits by single fault test sets”, IEEE Trans. Comput., vol. 0–30, pp. 855–865, November 1981.

    Article  Google Scholar 

  4. F.J.0. Dias, “Fault masking in combinational logic circuits”, IEEE Trans. Comput., vol. C-24, pp. 476–482, May 1975.

    Google Scholar 

  5. H. Fleisher and L.I. Maissel, “An introduction to array logic”,IBM J. Res. Develop., vol. 19, pp. 98–109, March 1975.

    Google Scholar 

  6. M. Fridrich and W.A. Davis, “Minimal fault tests for combinational networks”, IEEE Trans. Comput., vol. C-23,pp. 850–859, August 1974.

    Google Scholar 

  7. J.W.Gault, J.P.Robinson and S.M.Reddy,“Multiple Fault detection in combinational networks”,IEEE Trans. Comput., vol. 0–21, pp. 31–36, January 1972.

    MathSciNet  Google Scholar 

  8. L.H.Goldstein,“A probabilistic analysis of multiple faults in LSI circuits”, IEEE Comput. Repistory, R-77–304, IEEE Comput. Soc., Long Beach, CA.

    Google Scholar 

  9. J.Khakbaz,“A testable PLA design with low overhead and high fault coverage”, in Proc. FTCS-13, Milano, Italy 1983.

    Google Scholar 

  10. D.L.Ostapko and S.J.Hong,“Fault analysis and test generation for programmable logic arrays”, IEEE Trans. Comput., vol.C-28,pp. 617626, September 1979.

    Google Scholar 

  11. J.Rajski and J.Tyszer,“Fault influence function for identification bf multiple faults in combinational circuits”, in Proc. FTCS-13, Milano, Italy 1983, pp.106–109.

    Google Scholar 

  12. J.Rajski and J.Tyszer,“Combinatorial approach to multiple contact faults coverage in Programmable Logic Arrays”, accepted to IEEE Trans. Comput..

    Google Scholar 

  13. J.E.Smith,“On necessary and sufficient conditions for multiple fault undetectability”, IEEE Trans. Comput., vol.0–28, pp.801–802, October 1979.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1984 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Rajski, J., Tyszer, J. (1984). The Detection of Small Size Multiple Faults by Single Fault Test Sets in Programmable Logic Arrays. In: Großpietsch, KE., Dal Cin, M. (eds) Fehlertolerierende Rechensysteme. Informatik-Fachberichte, vol 84. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-69698-5_34

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-69698-5_34

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-13348-3

  • Online ISBN: 978-3-642-69698-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics