Abstract
Die Wafer Scale Integration erlaubt die monolithische Integration kompletter Systeme. Es wird ein SIMD Prozessor-Array mit ca. 10000 Knoten beschrieben, das in Wafer Scale Technik gefertigt wird. Ein Knotenprozessor enthält sechs ein-Bit Register, eine ein-Bit ALU und 128 Bits RAM. Zur Erzielung von Defekttoleranz wird eine zweistufige Hierarchie mit unterschiedlichen Rekonfigurierungskonzepten verwendet. Anwendungen eines solchen SIMD-Arrays ergeben sich in der Echtzeitbildverarbeitung und bei assoziativen Prozessoren.
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© 1988 Springer-Verlag Berlin Heidelberg
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Glesner, M., Huch, M., Ivey, P.A., Midwinter, T., Saucier, G., Trilhe, J. (1988). Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. In: Valk, R. (eds) GI — 18. Jahrestagung II. Informatik-Fachberichte, vol 188. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-74135-7_5
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DOI: https://doi.org/10.1007/978-3-642-74135-7_5
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