Scan technology at work

Summary

Scan technology is at least twenty years old and yet there is still reluctance to adopt its discipline. The presentation is about the requirements and practical implementation of scan - both internal and boundary (external).

Electronic product manufacturers - chip, board and system - are now conscious of the need to produce a product with the quality image. Quality has been defined as “meeting or exceeding the expectation of the user”. In reality, this means careful control of the absolute number of defects introduced into the product by the processes of design (non-conformance to specification) and manufacture (incorrect behaviour caused by the unwanted introduction of manufacturing inaccuracies). Such considerations give rise to the so-called “zero defect” and “zero escape” programs, and automatic testers play a vital role in monitoring quality parameters such as first-pass yield and failure rates.

Unfortunately, it is possible for a tester to fail a good product (because the tester has been programmed incorrectly), and to pass a bad product (inadequate fault coverage). The former represents inefficiency whereas the latter represents an escape. Products that fail are analysed to determine the cause of failure in order to fix the design process, fix the manufacturing process, fix the product itself, or fix the test environment according to the result of the analysis. Products that escape are either discovered later in the test cycle or “escape” to the final end user (who, in effect, becomes the final tester!).

Zero defect and zero escape programs are designed to reduce the incidence of “Pass, not OK”, “Fail, not OK”, and “Fail, OK” events. To implement such programs, the test programmer must be able to create test programs with, ideally, 100% defect coverage (to reduce escape rates to 0), and with excellent fault location properties in the event of test failure (to assist the “fix the product/process/program” activities).

Scan architectures are shown to support such requirements and internal scan architectures, such as LSSD, have been adopted by many organisations as the default method of design.

More recently, the advent of surf ace-mount technology coupled with multi-layer boards has caused the emergence of the ANSI/IEEE Standard 1149.1 standard on boundary scan. The presentation will survey and summarise the status of this new standard.