Abstract
Today there are many approaches and corresponding tools for supporting automatic design of large processor arrays. However, aspects of fault tolerance are generally neglected in array compilers or only taken into consideration after processor architecture synthesis. This paper discusses new approaches facilitating fault/defect-tolerant array processor design already during the mapping process. An especially suited methodology seems to be fault tolerance via idle processor elements which will be applied to a small example for explanation. Another advantage of that approach lies in the fact that idle processors can also be used to perform self-checking tasks such that overall processor utilization can become very high.
This research was sponsored by the EEC through basic research action BRA 3281 (ASCIS)
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Poechmueller, P., Glesner, M. (1991). A New Approach for Designing Fault-Tolerant Array Processors. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_27
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DOI: https://doi.org/10.1007/978-3-642-76930-6_27
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