A Fault Tolerant Interconnection Network for Memory-Coupled Multiprocessor Systems

Abstract

In this paper a concept for mapping a logical torus topology onto a physical interconnection structure will be presented. This kind of realization will obtain a reduction of the number of necessary communication paths by using additional dynamic network components. Therefore the hardware complexity for the interconnection network of a memory-coupled multiprocessor system can be reduced. The employment of such network components will yield additional aspects of fault tolerance given by the structure of the network component itself and the interconnection structure of the multiprocessor system which results when such network components are used. The primary subject of this paper will be the mechanisms of the interconnection network provided at hardware level. Therefore these mechanisms can be utilized time efficiently by the user or the operating system for instance for fault tolerance purposes.