Abstract
In this paper a proposal for an architecture of a general purpose watchdog processor is made. This watchdog processor monitors the behavior of the main processor by checking the control flow of processes using the Extended Signature Integrity Checking method (ESIC). The watchdog processor is independent of the architecture of the main processor because it is linked to the main processor by a memory interface.
The watchdog processor is well usable for multiprocessor systems based on standard components and a RISC/CISC processor with large cache as main processor. For the usage in multiprocessor systems the watchdog processors have their own communication network to exchange diagnosis information. As example for the distributed shared memory multiprocessor system MEMSY the realization of this system-level error detection mechanism is shown.
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References
Andrews, D. M.: Using Executable Assertions for Testing and Fault-Tolerance, Proc. 9th FTCS, 102–105, 1979
Daniels, S. F.: A Concurrent Test Technique for Standard Microprocessors, Dig. Papers Compcon Spring 83, 389–394, 1983
Eifert, J. B.; Shen, J. P.: Processor Monitoring Using Asynchronous Signatured Instruction Streams, Proc. 14th FTCS, 394–399, 1984
Fritsch, G.; Henning, W.; Hessenauer, H.; Klar, R.; Linster, C.U.; Oehlrich, C.W.; Schlenk, P.; Volkert, J.: Distributed Shared Memory Multiprocessor Architecture MEMS Y for High Performance Parallel Computations, ACM Computer Architecture News, vol$117, no. 6,22–35, 1989
Hackbusch, W. et. al.: Multigrid Methods, Proceedings of the Conference held at Cologne, Nov 23–27,1981, Springer Verlag, Berlin 1982
Hildebrand, U.: Transputer-basiertes Testsystem für Verbindungsnetzwerke speichergekoppelter Multiprozessoren, Workshop über Parallelverarbeitung, Segau, June 24.–30., 1990
Hönig, J.: Implementierung eines Präprozessors zur Generierung von Watchdogprogrammen, Diplomarbeit, IMMD in, Uni-Erlangen, 1990
Horton, G.: Parallel Solution of the Navier-Stokes Equations in Complex Geometries; NNFM Vol. 31, pp. 120–128; Vieweg, Braunschweig 1991
Lehmann-Emilius, L.: Rekonfiguration und Rückwärtsfehlerbehebung für Multiprozessoren mit begrenzter Nachbarschaft - eine Untersuchung zur verteilten Recovery, Dissertationsschrift, Arbeitsberichte des IMMD, Uni-Erlangen, Bd. 23, No. 2, 1990
Lu, D. J.: Watchdog Processors and Structural Integrity Checking, IEEE,T.o.C., 31 /7, 681–685, 1982
Mahmood, A; McCluskey, E. J.: Concurrent Error Detection Using Watchdog Processors - A Survey, IEEE,T.o.C., 37 /2, 160–174, 1988
Namjoo, M.: Cerberus-16: An Architecture for a General Purpose Watchdog Processor, Proc. 13th FTCS, 216–219, 1983
Namjoo, M.; McCluskey, E. J.: Watchdog Processors and Capability Checking, Proc. 12th FTCS, 245–248, 1982
Schuette, M. A.; Shen, J. P.: Processor Control Flow Monitoring Using Signatured Instruction Streams, IEEE T.o.C., 36 /2, 264–275, 1987.
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© 1991 Springer-Verlag Berlin Heidelberg
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Michel, E., Hohl, W. (1991). Concurrent Error Detection Using Watchdog Processors in the Multiprocessor System MEMSY. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_5
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DOI: https://doi.org/10.1007/978-3-642-76930-6_5
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