Abstract
In this paper we present a tool for hierarchical layout verification. Design rule check and netlist extraction can be performed within one program run. This allows to verify more complex rules than with separated tools and avoids redundant work. To improve verification, the program preserves the original layout hierarchy: Each cell in the layout is checked only once and then replaced by an abstract, containing all information needed to check the cell against its environment on the next higher level. The program does not require restrictions concerning the layout style, however the implemented basic algorithm can be modified by user instructions to adapt it to a special design style and thereby increasing its efficiency.
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© 1990 Springer-Verlag Berlin Heidelberg
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Meier, W. (1990). Hierarchical Netlist Extraction and Design Rule Check. In: Reusch, B. (eds) Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme. Informatik—Fachberichte, vol 255. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-84304-4_2
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DOI: https://doi.org/10.1007/978-3-642-84304-4_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-53163-0
Online ISBN: 978-3-642-84304-4
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