Abstract
The interest in research and implementations of type-2 fuzzy controllers (GlossaryTerm
T2FC
s) is increasing. It has been demonstrated that these controllers provide more advantages in handling uncertainties than type-1 FCs (GlossaryTermT1FC
s). This characteristic is very appealing because real-world problems are full of inaccurate information from diverse sources. Nowadays, it is no problem to implement an intelligent controller (GlossaryTermIC
) for microcomputers since they offer powerful operating systems, high-level languages, microprocessors with several cores, and co-processing capacities on graphic processing units (GlossaryTermGPU
s), which are interesting characteristics for the implementation of fast type-2 GlossaryTermIC
s (GlossaryTermT2IC
s). However, the above benefits are not directly available for the design of embedded GlossaryTermIC
s for consumer electronics that need to be implemented in devices such as an application-specific integrated circuit (GlossaryTermASIC
), a field-programmable gate array (GlossaryTermFPGA
s), etc. Fortunately, for GlossaryTermT1FC
s there are platforms that generate code in GlossaryTermVHSIC
hardware description language (GlossaryTermVHDL
; GlossaryTermVHSIC
: very high speed integrated circuit), C++, and Java. This is not true for the design of GlossaryTermT2IC
s, since there are no specialized tools to develop the inference system as well as to optimize it.The aim of this chapter is to present different ways of achieving high-performance computing for evolving GlossaryTerm
T1
and GlossaryTermT2
GlossaryTermIC
s embedded into GlossaryTermFPGA
s. Therefore, we provide a compiled introduction to GlossaryTermT1
and GlossaryTermT2
FCs, with emphasis on the well-known bottle neck of the interval GlossaryTermT2FC
(GlossaryTermIT2FC
), and software and hardware proposals to minimize its effect regarding computational cost. An overview of learning systems and hosting technology for their implementation is given. We explain different ways to achieve such implementations: at the circuit level using a hardware description language, using a multiprocessor system and a high-level language, and combining both methods. We explain how to use the GlossaryTermIT2FC
developed in GlossaryTermVHDL
as a standalone system, and as a coprocessor for the GlossaryTermFPGA
Fusion of Actel, Spartan , and Virtex . We present the methodology and two new proposals to achieve evolution of the GlossaryTermIT2FC
for GlossaryTermFPGA
, one for the static region of the GlossaryTermFPGA
, and the other one for the reconfigurable region using the dynamic partial reconfiguration methodology.Access this chapter
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Abbreviations
- ADC:
-
analog digital converter
- ALU:
-
arithmetic unit
- API:
-
application programming interface
- ASIC:
-
application-specific integrated circuit
- BSB:
-
base system builder
- CF:
-
compact flash
- CLB:
-
configurable logic block
- clk:
-
clock
- CMOS:
-
complementary metal-oxide-semiconductor
- COGIN:
-
coverage-based genetic induction
- CR:
-
control register
- CUDA:
-
compute unified device architecture
- CW:
-
control word
- DC/AD:
-
change/activate-deactivate
- DPR:
-
dynamic partial reconfiguration
- DSP:
-
digital signal processing
- DW:
-
data word
- EA:
-
evolutionary algorithm
- EAPR:
-
early access partial reconfiguration
- EFRBS:
-
evolutionary FRBS
- EKMANI:
-
enhanced Karnik–Mendel algorithm with new initialization
- EKM:
-
enhanced KM
- EODS:
-
enhanced opposite directions searching
- ES:
-
embedding system
- FIS:
-
fuzzy inference system
- FlexCo:
-
flexible coprocessor
- FL:
-
fuzzy logic
- FOU:
-
footprint of uncertainty
- FPGA:
-
field programmable gate array
- FRBS:
-
fuzzy rule-based system
- FS:
-
fuzzy set
- GA:
-
genetic algorithm
- GPGPU:
-
general-purpose GPU
- GPIO:
-
general-purpose input/output interface
- GPU:
-
graphics processing unit
- GT2:
-
generalized T2FS
- HDL:
-
hardware description language
- HPC:
-
high-performance computing
- HW:
-
hardware
- HWICAP:
-
hardware internal configuration access point
- IASC:
-
iterative algorithm with stop condition
- ICAP:
-
internal configuration access point
- IC:
-
intelligent controller
interrupt controller
- IE:
-
inference engine
- IOB:
-
input/output block
- IPIF:
-
intellectual property interface
- IP:
-
intellectual property
- ISE:
-
Integrated Synthesis Environment
- IT2FC:
-
interval T2FC
- IT2FS:
-
interval T2FS
- IT2:
-
interval type-2
- KM:
-
Karnik–Mendel
- LB:
-
logic block
- LT:
-
linguistic term
- LUT:
-
look-up table
- LV:
-
linguistic variable
- LVT:
-
linguistic-variable-term
- MF:
-
membership function
- MPS:
-
multiprocessor system
- OPB:
-
on-chip peripheral bus
- PAR:
-
place and route
- PD:
-
proportional-differential
- PLA:
-
programmable logic array
- PLB:
-
processor local bus
- PRM:
-
partially reconfigurable module
- PR:
-
partial reconfiguration
- PRR:
-
partially reconfigurable region
- RAM:
-
random access memory
- REGAL:
-
relational genetic algorithm learner
- RGN:
-
random generation number
- RISC:
-
reduced intstruction set computer
- ROM:
-
read only memory
- rst:
-
reset
- RTL:
-
register transfer logic
- RT:
-
real-time
- S-bit:
-
section-bit
- SPR:
-
static partial reconfiguration
- SW:
-
software
- T1FC:
-
type-1 fuzzy controller
- T1FS:
-
type-1 fuzzy set
- T1:
-
type-1
- T2FC:
-
type-2 fuzzy controller
- T2FS:
-
type-2 fuzzy set
- T2IC:
-
type-2 intelligent controller
- T2MF:
-
type-2 membership function
- T2:
-
type-2
- TR:
-
type reducer
- UART:
-
universal asynchronous receiver/transmitter
- UCF:
-
user constraint file
- VHDL:
-
VHSIC hardware description language
- VHSIC:
-
very high speed integrated circuit
- WT:
-
Wu–Tan
- XPS:
-
Xilinx platform studio
- XSG:
-
Xilinx system generator
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Montiel Ross, O.H., Sepúlveda Cruz, R. (2015). Evolving Embedded Fuzzy Controllers. In: Kacprzyk, J., Pedrycz, W. (eds) Springer Handbook of Computational Intelligence. Springer Handbooks. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-43505-2_76
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