Abstract
Emerging devices promise energy-efficient computing on a massively parallel scale, but due to the extremely high integration density the previously insignificant dissipation due to information erasure (destruction) becomes a prominent circuit design factor. The amount of heat generated by erasure depends on the degree of logical reversibility of the circuits and successful adiabatic charging. In this paper, we design an adiabatic arithmetic-logic unit to prototype the locally-connected Bennett-clocked circuit design approach. The results indicate one or two orders-of-magnitude energy savings in this physical circuit implementations vs. standard static CMOS. Previous work on computer arithmetic suggests that common hardware implementations erase much more information than would be required by a theoretical minimal mapping of the addition operation. A Bennett-clocked approach can reach the theoretical minimum number of bit erasures in the binary addition, though simulations show that a transistor technology has energy loss due to parasitic components that can exceed the information loss heat. In this paper, we describe the relationship between adiabatic and logically reversible circuits, and predict the potential of the arithmetic implementations based on quantum-dot cellular automata, which enable the full benefits of reversible, locally connected circuits to be realized.
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References
International Technology Roadmap for Semiconductors. ITRS report [Online] (2012). http://www.itrs.net/Links/2012ITRS/Home2012.htm
Lent, C., Tougaw, P.: A device architecture for computing with quantum dots. Proc. IEEE 85(4), 541–557 (1997)
Timler, J., Lent, C.: Maxwell’s demon and quantum-dot cellular automata. J. Appl. Phys. 94, 1050–1060 (2003)
Hänninen, I., Takala, J.: Binary adders on quantum-dot cellular automata. J. Sig. Proc. Syst. 58(1), 87–103 (2010)
Hänninen, I., Takala, J.: Binary multipliers on quantum-dot cellular automata. Facta Universitatis 20(3), 541–560 (2007)
Hänninen, I., Takala, J.: Irreversible bit erasures in binary adders. In: Proceedings of the 10th IEEE Conference on Nanotechnology, Seoul, Republic of Korea, 17–20 August 2010, pp. 223–226 (2010)
Hänninen, I., Takala, J., Lent, C.: Irreversible bit erasures in binary multipliers. In: Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 15–18 May 2011, pp. 2369–2372 (2011)
Hänninen, I., Takala, J.: Irreversibility induced density limits and logical reversibility in nanocircuits. In: Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, 4–6 July 2012
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183–191 (1961)
Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of Landauer’s principle linking information and thermodynamics. Nature 483, 187–189 (2012). http://dx.doi.org/10.1038/nature10872
Valiev, K.A., Starosel’skii, V.I.: A model and properties of a thermodynamically reversible logic gate. Russian Microelectron. 29(2), 83–98 (2000)
Younis, S.G.: Asymptotically zero energy computing using split-level charge recovery logic. Ph.D. thesis (1994). http://dspace.mit.edu/handle/1721.1/7058
Starosel’skii, V.I.: Adiabatic logic circuits: a review. Russian Microelectron. 31(1), 37–58 (2002)
Lim, J., Kim, D.-G., Chae, S.-I.: Reversible energy recovery logic circuit and its 8-phase clocked power generator for ultra-low-power applications. IEICE Trans. Electron. E82-C(4), 646–653 (1999)
Lim, J., Kim, D.-G., Chae, S.-I.: nMOS reversible energy recovery logic for ultra-low-energy applications. IEEE J. Solid-State Circuits 35(6), 865–875 (2000)
Yibin, Y., Roy, K.: Energy recovery circuits using reversible and partially reversible logic. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 43(9), 769–778 (1996). doi:10.1109/81.536746
Dueck, G.W.: Synthesis of Toffoli Networks: status and challenges. In: International Symposium on Electronic System Design (ISED), 19–22 December 2012, pp. 11–16 (2012). doi:10.1109/ISED.2012.26
Lent, C.S., Liu, M., Lu, Y.: Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling. Nanotechnology 17(16), 4240–4251 (2006)
Bennett, C.: Logical reversibility of computation. IBM J. Res. Dev. 17, 525–532 (1973)
Texas Instruments Inc.: The TTL Data Book for Design Engineers, 2nd edn, pp. 7-484–7-486. Texas Instruments Inc., Dallas (1976)
Vladimirescu, A., Liu, S.: The simulation of MOS integrated circuits using SPICE2. Technical report no. UCB/ERL M80/7, University of California, Berkeley (1980)
Arizona State University Predictive Technology Model (PTM) Website [Online]. http://ptm.asu.edu
Weinstein, D., Bhave, S.A.: The resonant body transistor. Nano Lett. 10(4), 1234–1237 (2010). doi:10.1021/nl9037517
Hänninen, I., Lent, C.S., Snider, G.L.: Models of irreversibility for binary adders. In: Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Invited paper, Columbus, OH, USA, 4–7 August 2013, pp. 1071–1074 (2013)
Acknowledgments
The authors wish to thank the organizers and attendees of the Workshop on Field-Coupled Nanocomputing, February 7–8, 2013, Tampa, Florida, USA, for their suggestions and constructive critique on the design of emerging reversible circuits. This work was supported by the Academy of Finland under research grant 132869 and the Finnish Foundation for Technology Promotion.
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Hänninen, I., Lu, H., Blair, E.P., Lent, C.S., Snider, G.L. (2014). Reversible and Adiabatic Computing: Energy-Efficiency Maximized. In: Anderson, N., Bhanja, S. (eds) Field-Coupled Nanocomputing. Lecture Notes in Computer Science(), vol 8280. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-43722-3_14
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