Skip to main content

Energy Efficiency Evaluation of Workload Execution on Intel Xeon Phi Coprocessor

  • Conference paper
  • First Online:
  • 1213 Accesses

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 426))

Abstract

Although the performance of multi-core processor continues to increase steadily, power consumption with core density at such high level gradually becomes a limiting factor for computing facilities hosting massive servers to expand at even larger scale, especially as we entering the era of many core architecture. In spite of various power management techniques already existed for year, none of them has ever been demonstrated feasible on the real many core platforms since it is until recently the Intel Xeon Phi processor realizes the prospect of many core architecture into product. Along with the Xeon Phi processor, the power management capability has been significantly improved with hardware and software support that the user could analyze the power consumption of the application at fine granularity with sufficient information captured during the runtime by the power monitoring infrastructures implemented on Xeon Phi processor. However, at the time we propose this study, there is no comprehensive investigation to evaluate the power and energy properties of such many core platform when running diverse applications despite of the performance boost.

In this paper, we leverage representative benchmark suites including various parallel workloads, running with OpenMP mode, from diverse domains to evaluate the MIC architecture. With the power measurement ability exposed by Power Management and SCIF interface, the energy can be tracked every 50 ms. The experiments reveal non-intuitive results on the impact of MIC in terms of energy efficiency: (1) for computation intensive workload such as BT and FT in NPB, MC and MD in SHOC, in contrast to our expectation, MIC doesn’t keep improving the system energy efficiency with the increasing threads; (2) for memory intensive application such as IS in NPB and DeviceMemory in SHOC, MIC actually deteriorates the system energy efficiency significantly; (3) for EPCC, which is used to investigate overheads of key OpenMP constructs, the workloads suffer energy efficiency decline mostly caused by the high pressures from the communication among cores.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Intel Corporation. Intel Many Integrated Core Architecture (Intel MIC Architecture) C Advanced (2013). http://www.intel.com/content/www/us/en/architecture-and-technology/many-integrated-core/intel-many-integrated-core-architecture.html

  2. Intel Many Integrated Core Symmetric Communications Interface (SCIF) User Guide. Technical report, Revision 1.01, Intel Corporation (2013)

    Google Scholar 

  3. Intel Xeon Phi Coprocessor System Software Developers Guide. Technical report, SKU 328207-001EN, Intel Corporation (2013)

    Google Scholar 

  4. Jin, H., Frumkin, M., Yan, J.: The OpenMP implementation of NAS parallel benchmarks and its performance. Technical report, NAS-99-011, NASA Ames Research Center (1999)

    Google Scholar 

  5. Danalis, A., Marin, G., McCurdy, C., Meredith, J.S., Roth, P.C., Spafford, K., Tipparaju, V., Vetter, J.S.: The scalable heterogeneous computing (SHOC) benchmark suite. In: Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, pp. 63–74. ACM (2010)

    Google Scholar 

  6. Mark Bull, J., O’Neill, D.: A microbenchmark suite for OpenMP 2.0. SIGARCH Comput. Archit. News 29(5), 41–48 (2001)

    Article  Google Scholar 

  7. Cramer, T., Schmidl, D., Klemm, M., an Mey, D.: OpenMP programming on Intel Xeon Phi coprocessors: an early performance comparison. In: Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, pp. 38–44, November 2012

    Google Scholar 

  8. Vienne, J., Ramachandran, A., Wijngaart, R., Koesterke, L., Shaparov, I.: Performance evaluation of NAS parallel benchmarks on Intel Xeon Phi. In: 6th International Workshop on Parallel Programming Models and Systems Software for High-End Computing (2013)

    Google Scholar 

  9. Misra, G., Kurkure, N., Das, A., Valmiki, M., Das, S., Gupta, A.: Evaluation of rodinia codes on Intel Xeon Phi. In: 2013 4th International Conference on Intelligent Systems Modelling Simulation (ISMS), pp. 415–419 (2013)

    Google Scholar 

  10. Shao Y.S., Brooks, D.: Energy characterization and instruction-level energy model of Intel’s Xeon Phi processor. In: 2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 389–394 (2013)

    Google Scholar 

Download references

Acknowledgments

This work was supported by the National High Technology Research and Development Program (“863” Program) of China under the grant No.2012AA010904.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Qi Zhao .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Zhao, Q., Yang, H., Wei, G., Luan, Z., Qian, D. (2014). Energy Efficiency Evaluation of Workload Execution on Intel Xeon Phi Coprocessor. In: Yuan, Y., Wu, X., Lu, Y. (eds) Trustworthy Computing and Services. ISCTCS 2013. Communications in Computer and Information Science, vol 426. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-43908-1_34

Download citation

  • DOI: https://doi.org/10.1007/978-3-662-43908-1_34

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-662-43907-4

  • Online ISBN: 978-3-662-43908-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics