Abstract
This paper presents introduction for a QoS verification of on-chip interconnection based on the new progress of the industry, which combined with an AMD processor chip design for big data. Some verification experience in architectural modeling and simulation of on-chip interconnection is also introduced in this paper.
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Qinghua, L., Jilong, Q., Xu, D., Endong, W., Weifeng, G. (2015). An On-chip Interconnection QoS Verification Platform of Processor of Large Data for Architectural Modeling Analysis. In: Wang, H., et al. Intelligent Computation in Big Data Era. ICYCSEE 2015. Communications in Computer and Information Science, vol 503. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-46248-5_53
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DOI: https://doi.org/10.1007/978-3-662-46248-5_53
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-46247-8
Online ISBN: 978-3-662-46248-5
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