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RSA Encryption/Decryption Implementation Based on Zedboard

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Trustworthy Computing and Services (ISCTCS 2014)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 520))

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Abstract

This paper implements a 1024-bit RSA encryption/decryption system based on Zedboard, a product of Xilinx. It adopts some improved algorithms included limiting the intermediate product of multiplication and Chinese Remained Theorem(CRT) to improve the computing efficiency. It mainly optimizes the structure of system to satisfy the limited resource of Zedboard through the hardware-software codesign which makes the resource used effectively.

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References

  1. Su, F., Hwang, T.: Comments on iterative modular multiplication without magnitude comparison. In: Proceedings of the 6th National Conference on Information Security, pp. 21–22 (1996)

    Google Scholar 

  2. Chen, C.Y., Liu, T.C.: A fast modular multiplication method based on the lempel–ziv binary tree. Comput. Commun. 22(9), 871–874 (1999)

    Article  Google Scholar 

  3. Kaur, G., Arora, V.: An efficient implementation of RSA algorithm using FPGA and big prime digit. IJCCER 1(4), 100–103 (2013)

    Google Scholar 

  4. Sahu, S.K., Pradhan, M.: FPGA implementation of RSA encryption system. Int. J. Comput. Appl. 19(9), 10–12 (2011)

    Google Scholar 

  5. Anand, A., Praveen, P.: Implementation of RSA algorithm on FPGA. Int. J. Eng. Res. Technol. 1(5) (2012)

    Google Scholar 

  6. Ito, Y., Nakano, K., Bo, S.: The parallel FDFM processor core approach for CRT-based RSA decryption. Int. J. Netw. Comput. 2(1), 79–96 (2012)

    Google Scholar 

  7. Christofi, M., Chetali, B., Goubin, L.: Formal verification of an implementation of CRT-RSA vigilants algorithm. In: PROOFS Workshop: Pre-proceedings, p. 28 (2013)

    Google Scholar 

  8. Attili, S., Jain, S., Mitra, S.: PS and PL ethernet performance and jumbo frame support with PL ethernet in the Zynq-7000 AP SoC (2013)

    Google Scholar 

  9. Rao, G.R.C., Lakshmi, P., Shankar, N.R.: A new modular multiplication method in public key cryptosystem. IJ Netw. Secur. 15(1), 23–27 (2013)

    Google Scholar 

  10. Sutter, G.D., Deschamps, J., Imaña, J.L.: Modular multiplication and exponentiation architectures for fast RSA cryptosystem based on digit serial computation. IEEE Trans. Ind. Electron. 58(7), 3101–3109 (2011)

    Article  Google Scholar 

  11. Menezes, A.J., Van Oorschot, P.C., Vanstone, S.A.: Handbook of Applied Cryptography. CRC Press, Boca Raton (2010)

    Google Scholar 

  12. Quisquater, J.J., Couvreur, C.: Fast decipherment algorithm for RSA public-key cryptosystem. Electron. Lett. 18(21), 905–907 (1982)

    Article  Google Scholar 

  13. Kim, C., Ha, J.C., Kim, S.-H., Kim, S., Yen, S.-M., Moon, S.-J.: A secure and practical CRT-based RSA to resist side channel attacks. In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C., Gervasi, O. (eds.) ICCSA 2004. LNCS, vol. 3043, pp. 150–158. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  14. Rivest, R.L., Shamir, A., Adleman, L.: A method for obtaining digital signatures and public-key cryptosystems. Commun. ACM 21(2), 120–126 (1978)

    Article  MATH  MathSciNet  Google Scholar 

  15. Nedjah, N., Mourelle, L.M.: Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic. IEEE Trans. Circuits Syst. I: Regul. Pap. 53(3), 627–633 (2006)

    Article  MathSciNet  Google Scholar 

  16. Takagi, N., Yajima, S.: Modular multiplication hardware algorithms with a redundant representation and their application to RSA cryptosystem. IEEE Trans. Comput. 41(7), 887–891 (1992)

    Article  Google Scholar 

  17. Lu, J., Jiang, Z., Ma, M.: Embedded System Hardware and Software Co-design Practical Guide based on XilinxZynq. China Machine Press, Beijing (2013)

    Google Scholar 

  18. Wu, C.H., Hong, J.H., Wu, C.W.: RSA cryptosystem design based on the chinese remainder theorem. In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference, pp. 391–395. ACM (2001)

    Google Scholar 

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Acknowledgment

This study is supported by the Special Pilot Research of the Chinese Academy of Sciences (Grant No. XDA06030200).

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Correspondence to Lei Jiang .

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Bai, X., Jiang, L., Liu, X., Tan, J. (2015). RSA Encryption/Decryption Implementation Based on Zedboard. In: Yueming, L., Xu, W., Xi, Z. (eds) Trustworthy Computing and Services. ISCTCS 2014. Communications in Computer and Information Science, vol 520. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-47401-3_15

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  • DOI: https://doi.org/10.1007/978-3-662-47401-3_15

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-662-47400-6

  • Online ISBN: 978-3-662-47401-3

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