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The Improvement and Implementation of iSLIP Algorithm Based on FPGA

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Trustworthy Computing and Services (ISCTCS 2014)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 520))

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Abstract

High-efficiency scheduling algorithm ensures the high throughput rate of switching network and high utilization rate of bandwidth. In order to reduce the communication time delay and BER (Bit Error Rate) of data transmission, we improve the iSLIP scheduling algorithm and achieve a better performance of high speed switching system by using less FPGA resources.

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References

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Acknowledgement

This research is supported by the Fundamental Research Funds for the Central Universities (No.FRF-TP-14-046A2), and also supported by the National Natural Science Foundation of P. R. China (No.61102060).

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Correspondence to Zeng Guang .

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Guang, Z., Lin, Y., Ming, Z., Yilan, M. (2015). The Improvement and Implementation of iSLIP Algorithm Based on FPGA. In: Yueming, L., Xu, W., Xi, Z. (eds) Trustworthy Computing and Services. ISCTCS 2014. Communications in Computer and Information Science, vol 520. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-47401-3_34

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  • DOI: https://doi.org/10.1007/978-3-662-47401-3_34

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-662-47400-6

  • Online ISBN: 978-3-662-47401-3

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