Abstract
The property of addresses accessed by one butterfly in FFT processors arises the difficulty for parallel accessing during computation. And the address reversal at input or output stage increases the difficulty for parallel I/O. In this paper, a new and simple generalized memory address transformation method supporting parallel accessing for computation is proposed to accelerate 2n-point Mixed-Radix FFT for memory-based FFT processors with SIMD extension. To make I/O clock cycles match up with computation cycles, a new I/O addresses parallel generation method is also proposed. The advantages of the method proposed in this paper lie in the fact that they support the maximum throughput SIMD memory with multi-bank structures and in-place policy for both I/O and computation with continuous data flow. And most importantly, the address transformation circuit for FFT computations is low-complexity with only XOR gates; the I/O addresses parallel generation circuit is also simple with just counters.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Hsiao, C.F., Chen, Y., Lee, C.Y.: A generalized mixed-radix algorithm for memory-based FFT processors. IEEE Trans. Circuits Syst. II Exp. Briefs 57(1), 26–30 (2010)
Ma, Y.: An effective memory addressing scheme for FFT processors. IEEE Trans. Signal Process. 47(3), 907–911 (1999)
Lin, Y.T., Tsai, P.Y., Chiueh, T.D.: Low-power variable-length fast Fourier transform processor. IEEE Proc. Comput. Digit. Technol. 152(4), 499–506 (2005)
Lin, Y.W., Lee, C.Y.: Design of an FFT/IFFT processor for MIMO-OFDM systems. IEEE Trans. Circuits Syst. I, Regul. Pap. 54(4), 807–815 (2007)
Lin, Y.W., Liu, H.Y., Lee, C.Y.: A dynamic scaling FFT processor for DVB-T applications. IEEE J. Solid State Circuits 39(11), 2005–2013 (2004)
Jo, B.G., Sunwoo, M.H.: New continuous- flow mixed-radix(CFMR) FFT processor using novel in-place strategy. IEEE Trans. Circuits Syst. I, Regul. Pap. 52(5), 911–919 (2005)
Reisis, D., Vlassopoulos, N.: Conflict-free parallel memory accessing techniques for FFT architectures. IEEE Trans. Circuits Syst. I, Regul. Pap. 55(11), 3438–3447 (2008)
Takala, J.H., Jarvinen, T., Sorokin, H.: Conflict-free parallel memory access scheme for FFT processors. In: Proceedings of International Symposium on Circuits and Syst. (ISCAS 2003), vol. 4, 524–527. IEEE (2003)
Sorokin, H., Takala, J.: Conflict-free parallel access scheme for mixed-radix FFT supporting I/O permutations. In: Proceedings of IEEE International Conference on Acoustics, Speech, Signal Processing, pp. 1709–1712 (2011)
Hidalgo, J.A., Lopez, J., Arguello, F., Zapata, E.L.: Area-efficient architecture for fast Fourier transform. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 46(2), 187–193 (1999)
Jacobson, A.T., Truong, D.N., Baas, B.M.: The design of a reconfigurable continuous-flow mixed-radix FFT processor. In: Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1133–1136 (2009)
Takai, R., Uchida, S., Sato, A., Sanada, Y.: Experimental investigation of signal sensing with overlapped FFT based energy detection. Wireless Pers. Commun. 77(1), 553–569 (2014)
Norouzi, P., Alahdadi, I., Shahtaheri, S.J.: Determination of ochratoxin at nanocomposite modified glassy carbon electrode combine with FFT coulometric admittance voltammetry and flow injection analysis. Int. J. Electrochem. Sci. 10, 3400–3413 (2015)
Wang, Z., Liu, X., He, B., Yu, F.: A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT. IEEE Trans. VLSI Syst. 23, 973–977 (2015)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yang, C., Chen, H., Liu, S., Ma, S. (2016). A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension. In: Xu, W., Xiao, L., Li, J., Zhang, C. (eds) Computer Engineering and Technology. NCCET 2015. Communications in Computer and Information Science, vol 592. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-49283-3_6
Download citation
DOI: https://doi.org/10.1007/978-3-662-49283-3_6
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-49282-6
Online ISBN: 978-3-662-49283-3
eBook Packages: Computer ScienceComputer Science (R0)
