Skip to main content

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 202))

Abstract

In this paper, we study and evaluate fault-tolerant technology for use in the parallel acceleration of evolutionary computation on many-core processors. Specifically, we show running evolutionary computation in parallel on a GPU results in a system that not only performs better as the number of processor cores increases, but is also robust against any physical faults (e.g., stuck-at faults) and transient faults (e.g., faults caused by noise), and makes it less likely that the application program will be interrupted while running. That is, we show that this approach is beneficial for the implementation of systems with sustainability.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  • [1] Mühlenbein, H.: Evolution in time and space - the parallel genetic algorithm. In Foundations of Genetic Algorithms, pp. 316–337. Morgan Kaufmann (1991).

    Google Scholar 

  • [2] Shonkwiler, R.: Parallel genetic algorithm. In Proc. of the 5th International Conference on Genetic Algorithms, pp. 199–205 (1993).

    Google Scholar 

  • [3] Pham, D., Asano, S., Bolliger, M., Day, M. N., Hofstee, H. P., Johns, C., Kahle, J., Kameyama, A, Keaty, J., Masubuchi, Y., Riley, M., Shippy, D., Stasiak, D., Suzuoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yamazaki, T., and Yazawa, K.: The design and implementation of a first-generation CELL processor. In 2005 IEEE International Solid- State Circuits Conference, vol. 1, pp. 184–592 (2005).

    Google Scholar 

  • [4] Shiota, T., Kawasaki, K., Kawabe, Y., Shibamoto, W., Sato, A., Hashimoto, T., Hayakawa, F., Tago, S., Okano, H., Nakamura, Y., Miyake, H., Suga, A., and Takahashi, H.: A 51.2 gops 1.0 gb/sdma single-chip multi-processor integrating quadruple 8-way vliw processors. In 2005 IEEE International Solid-State Circuits Conference, vol. 1, pp. 194–593 (2005).

    Google Scholar 

  • [5] Torii, S., et al.: A 600mips 120mw 70ua leakage triple-cpu mobile application processor chip. In the IEEE ISSCC Digest of Technical Papers, pp. 136–137 (2005).

    Google Scholar 

  • [6] Byun, J.-H., Datta, K., Ravindran, A., Mukherjee, A., and Joshi, B.: Performance analysis of coarse-grained parallel genetic algorithms on the multi-core sun UltraSPARC T1. In SOUTHEASTCON’09. IEEE, pp. 301–306 (2009).

    Google Scholar 

  • [7] Serrano, R., Tapia, J., Montiel, O., Sep´ulveda, R., and Melin, P.: High performance parallel programming of a GA using multi-core technology. In Soft Computing for Hybrid Intelligent Systems, pp. 307–314 (2008).

    Google Scholar 

  • [8] Tsutsui, S., and Fujimoto, N.: Solving quadratic assignment problems by genetic algorithms with GPU computation: a case study. In Proceedings of the 2009 ACM/SIGEVO Genetic and Evolutionary Computation Conference, pp. 2523–2530 (2009).

    Google Scholar 

  • [9] Sato, M., Sato, Y., and Namiki, M.: Proposal of a multi-core processor from the viewpoint of evolutionary computation. In Proceedings of the 2010 IEEE Congress on Evolutionary Computation, CD-ROM (2010).

    Google Scholar 

  • [10] Sato, Y., Hasegawa, N., and Sato, M.: GPU Acceleration for Sudoku Solution with Genetic Operations. In Proceedings of the 2011 IEEE Congress on Evolutionary Computation, CD-ROM (2011).

    Google Scholar 

  • [11] Lara, P. K.: Fault Tolerant and Fault Testable Hardware Design. Prentice-Hall International Ltd (1985).

    Google Scholar 

  • [12] Toy, W. N., and Gallaher, L. E.: Overview and architecture of 3B20D processor. Bell Syst. Tech. J., Vol. 62, No. 1, pt. 2, pp. 181-19 (1983).

    Google Scholar 

  • [13] Bartlet, F.: The Tandem 16; A “NonStop” operating system. In The Theory and Practice of Reliable System Design (Ed. By D. P. Siewiorek and R. S. Searz), pp. 453-460 (1982).

    Google Scholar 

  • [14] Siewiorek, D. P., et al.: A case study of C.mmp, Cm and C.Vmp: Part 1 – Experience with fault-tolerance in multiprocessor systems. ibid., pp. 1178-1199 (1978).

    Google Scholar 

Download references

Acknowledgments

This research is partly supported by the collaborative research program 2012, Information Initiative Center, Hokkaido University, and a grant from the Institute for Sustainability Research and Education of Hosei University 2012.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yuji Sato .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer India

About this paper

Cite this paper

Sato, Y. (2013). Parallelization of Genetic Algorithms and Sustainability on Many-core Processors. In: Bansal, J., Singh, P., Deep, K., Pant, M., Nagar, A. (eds) Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012). Advances in Intelligent Systems and Computing, vol 202. Springer, India. https://doi.org/10.1007/978-81-322-1041-2_15

Download citation

  • DOI: https://doi.org/10.1007/978-81-322-1041-2_15

  • Published:

  • Publisher Name: Springer, India

  • Print ISBN: 978-81-322-1040-5

  • Online ISBN: 978-81-322-1041-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics