Abstract
The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. MTCMOS technique which decreases the process variation on 1-bit Full Adder, the key of MTCMOS technique is applied on 1-bit Full Adder is to reduce the operating power, leakage power and leakage current. We investigate the use Multi-threshold CMOS (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low Vth transistors for logic cells and low leakage, high Vth of transistor and show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 20 ns access time and frequency 0.05 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out 1-bit Full Adder.
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Saraswat, R., Akashe, S., Babu, S. (2013). Analysis and Simulation of Full Adder Design Using MTCMOS Technique. In: Bansal, J., Singh, P., Deep, K., Pant, M., Nagar, A. (eds) Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012). Advances in Intelligent Systems and Computing, vol 202. Springer, India. https://doi.org/10.1007/978-81-322-1041-2_16
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DOI: https://doi.org/10.1007/978-81-322-1041-2_16
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