Adaptive Multilayer Routing for Incremental Design of an SoC

Abstract

Intellectual properties (IPs) in design form are integrated for incremental design of system-on-chip (SoC). In order to realize proper functionality of an SoC, some global signal nets are often needed to be connected between the design IPs. If the component IPs are in-house, the global nets may be routed through the routing region of the design IPs and this routing may be formulated as an adaptive incremental routing problem where all the routing issues need to be tackled directly in the detailed routing phase only. In this work, we propose a technique for adaptive incremental routing of global nets with the objectives of minimal increase in wire length, congestion, and number of vias. The first objective maintains the desired frequency, the second and the third ones reduce the power overhead, and specifically the third one is effective in keeping the layout manufacture-friendly. The proposed technique is applied on some ISCAS’85 benchmarks and finally on a crypto SoC design which integrates several component designs for crypto-cores. The results on CPU time for routing and the overhead of routing are encouraging.