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FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems

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Dynamically Reconfigurable Systems

Abstract

Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This chapter presents a family of application-specific instruction-set processors (ASIPs) for channel coding in wireless communication systems. Flexibility is provided by offering not only programmability but also dynamical reconfiguration within the ASIP pipeline. As a weakly programmable IP core, it can implement many channel decoding schemes for a SDR environment. It features binary convolutional decoding, turbo decoding for binary as well as duo-binary turbo codes, and LDPC decoding for current and upcoming standards. The ASIP consists of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. A reconfigurable data shuffling allows for fast context switches, multi-standard support, and a efficient ASIP implementation.

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References

  1. Alles, M., Vogt, T., Wehn, N.: FlexiChaP: A reconfigurable ASIP for convolutional, Turbo, and LDPC code decoding. In: Proc. 5th International Symposium on Turbo Codes and Related Topics, Lausanne, Switzerland, pp. 84–89 (2008)

    Google Scholar 

  2. Alles, M., Lehnigk-Emden, T., Brehm, C., Wehn, N.: A rapid prototyping environment for ASIP validation in wireless systems. In: EDA Workshop 2009, Dresden, Germany (2009)

    Google Scholar 

  3. Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error-correcting coding and decoding: turbo-codes. In: Proc. 1993 International Conference on Communications (ICC ’93), Geneva, Switzerland, pp. 1064–1070 (1993)

    Google Scholar 

  4. Berrou, C., Jezequel, M., Doullard, C., Kerouedan, S.: The advantages of non-binary turbo codes. In: Proceedings of Information Theory Workshop, Cairns, Australia, pp. 61–63 (2001)

    Google Scholar 

  5. Boutillon, E., Castura, J., Kschischang, F.: Decoder-first code design. In: Proc. 2nd International Symposium on Turbo Codes & Related Topics, Brest, France, pp. 459–462 (2000)

    Google Scholar 

  6. Chen, J., Dholakia, A., Eleftheriou, E., Fossorier, M.P.C., Hu, X.Y.: Reduced-complexity decoding of LDPC codes. IEEE Trans. Commun. 53(8), 1288–1299 (2005)

    Article  Google Scholar 

  7. CoWare, http://www.coware.com

  8. Dawid, H.: Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany (1996). In German

    Google Scholar 

  9. Gallager, R.G.: Low-density parity-check codes. IRE Trans. Inf. Theory 8(1), 21–28 (1962)

    Article  MathSciNet  Google Scholar 

  10. Genode FPGA Graphics (FX), http://www.genode-labs.com/products/fpga-graphics

  11. Gilbert, F.: Optimized, highly parallel architectures for iterative decoding algorithms. PhD thesis, Microelectronic Systems Design Research Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern (2003). ISBN 3-936890-06-4

    Google Scholar 

  12. Glossner, J., Iancu, D., Moudgill, M., Nacer, G., Jinturkar, S., Schulte, M.: The Sandbridge SB3011 SDR platform. In: Joint IST Workshop on Mobile Future and the Symposium on Trends in Communications (SympoTIC ’06), pp. ii–v (2006)

    Google Scholar 

  13. IMEC: Scientific Report 2006: Software Defined Radio Flexible Air Interface. www.microelektronica.be/wwwinter/mediacenter/en/SR2006/681340.html (2006)

  14. Ituero, P., Lopez-Vallejo, M.: New schemes in clustered VLIW processors applied to turbo decoding. In: Application-specific Systems, Architectures and Processors, 2006. ASAP ’06. International Conference on, pp. 291–296 (2006). doi:10.1109/ASAP.2006.48

  15. Krishnaiah, G., Engin, N., Sawitzki, S.: Scalable reconfigurable channel decoder architecture for future wireless handsets. In: Proc. 2007 Design, Automation and Test in Europe (DATE ’07) (2007)

    Google Scholar 

  16. Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.: SODA: A low-power architecture for software radio. In: Proc. 33rd International Symposium on Computer Architecture (ISCA’06), pp. 89–101 (2006)

    Google Scholar 

  17. Lodi, A., Cappelli, A., Bocchi, M., Mucci, C., Innocenti, M., De Bartolomeis, C., Ciccarelli, L., Giansante, R., Deledda, A., Campi, F., Toma, M., Guerrieri, R.: XiSystem: a XiRisc-based SoC with reconfigurable IO module. IEEE J. Solid-State Circuits 41(1), 85–96 (2006). doi:10.1109/JSSC.2005.859319

    Article  Google Scholar 

  18. Mansour, M.M., Shanbhag, N.R.: VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), 627–650 (2003)

    Article  Google Scholar 

  19. Matu, E., Seidel, H., Limberg, T., Robelly, P., Fettweis, G.: A GFLOPS vector-DSP for broadband wireless applications. In: Conference 2006, IEEE Custom Integrated Circuits, pp. 543–546 (2006). doi:10.1109/CICC.2006.320923

  20. Michel, H., Worm, A., Münch, WehnN.: Hardware/software trade-offs for advanced 3G channel coding. In: Proc. 2002 Design, Automation and Test in Europe (DATE ’02), Paris, France (2002)

    Google Scholar 

  21. ML507 Evaluation Platform, http://www.xilinx.com/products/devkits/HW-V5-ML507-UNI-G.htm

  22. Muller, O., Baghdadi, A., Jezequel, M.: From parallelism levels to a multi-ASIP architecture for turbo decoding. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(1), 92–102 (2009)

    Article  Google Scholar 

  23. PACT XPP Technologies, www.pactcorp.com

  24. Reed, M.C., Pietrobon, S.S.: Turbo-code termination schemes and a novel alternative for short frames. In: Proc. 1996 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC ’96), Taipei, Taiwan, vol. 2, pp. 354–358 (1996)

    Google Scholar 

  25. Robertson, P., Hoeher, P., Villebrun, E.: Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding. European Transactions on Telecommunications (ETT) 8(2), 119–125 (1997)

    Article  Google Scholar 

  26. Stretch, http://www.stretchinc.com

  27. Viterbi, A.J.: Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. IEEE Trans. Inform. Theory IT-13, 260–269 (1967)

    Article  Google Scholar 

  28. Viterbi, A.J., Omura, J.K.: Principles of Digital Communication and Coding. McGraw–Hill, New York (1979)

    MATH  Google Scholar 

  29. Vogt, T., Wehn, N.: A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment. IEEE Trans. Very Large Scale Integrat. (VLSI) Syst. 16(10), 1309–1320 (2008)

    Article  Google Scholar 

  30. Vogt, T., Neeb, C., Wehn, N.: A reconfigurable multi-processor platform for convolutional and turbo decoding. In: Reconfigurable Communication-centric SoCs (ReCoSoC), Montpellier, France (2006)

    Google Scholar 

  31. Xilinx Inc., http://www.xilinx.com/ipcenter

  32. Yuan, L., Mahlke, S., Trevor, M., Chaitali, C., Alastair, R., Krisztian, F.: Design and implementation of turbo decoders for software defined radio. In: Proc. IEEE 2006 Workshop on Signal Processing Systems (SiPS) (2006)

    Google Scholar 

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Alles, M., Vogt, T., Brehm, C., Wehn, N. (2010). FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems. In: Platzner, M., Teich, J., Wehn, N. (eds) Dynamically Reconfigurable Systems. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3485-4_14

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  • DOI: https://doi.org/10.1007/978-90-481-3485-4_14

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