Abstract
A new concepts for run time reconfigurable systems called hyperreconfiguration is investigated in this project. Hyperreconfigurable architectures can dynamically change their reconfiguration potential to adapt to the current needs of a computation and therefore gauge high flexibility with high reconfiguration overhead against small flexibility with reduced overhead. Within this concept we also propose the use of multi-level reconfiguration where higher-level hyperreconfiguration operations define the flexibility of the system for reconfiguration while lower-level reconfiguration operations alter the system’s functionality within the limits set by the preceding hyperreconfigurations.
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References
Compton, K., Hauck, S.: Configurable computing: a survey of systems and software. ACM Comput. Surv. 34(2), 171–210 (2002)
Dandalis, A., Prasanna, V.K.: Configuration compression for FPGA-based embedded systems. In: Proc. ACM Int. Symp. on Field-Programmable Gate Arrays, pp. 173–182 (2001)
Hauck, S., Li, Z., Rolim, J.: Configuration compression for the Xilinx XC6200 FPGA. IEEE Trans. Comput.-Aided Des. 8, 1107–1113 (1999)
Kannan, P., Balachandran, S., Bhatia, D.: On metrics for comparing routability estimation methods for FPGAs. In: Proc. 39th Design Autom. Conf., pp. 70–75 (2002)
Koch, D., Teich, J.: Platform-independent methodology for partial reconfiguration. In: Proc. 1st Conference on Computing Frontiers, pp. 398–403 (2004)
Köster, M., Teich, J.: (Self-)reconfigurable finite state machines: Theory and implementation. In: Proc. Design. Autom. and Test in Europe, pp. 559–566 (2002)
Lange, S.: Hyperreconfigurable systems. Formal concepts, architectures, and applications. Dissertation (in German), Faculty of Mathematics and Computer Science, University of Leipzig (2008)
Lange, S., Kebschull, U.: Virtual hardware byte code as a design platform for reconfigurable embedded systems. In: Proc. DATe 03 (2003)
Lange, S., Middendorf, M.: Hyperreconfigurable architectures as flexible control systems. In: ARCS 2004 Workshop “Dynamically Reconfigurable Systems”. LNI, vol. P-41, pp. 175–184 (2004)
Lange, S., Middendorf, M.: Hyperreconfigurable architectures for fast runtime reconfiguration. In: Proc. 2004 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’04), pp. 304–305 (2004)
Lange, S., Middendorf, M.: Models and reconfiguration problems for multi task hyperreconfigurable architectures. In: Proc. Rec. Arch. Workshop (RAW 2004), p. 8 (2004)
Lange, S., Middendorf, M.: The partition into hypercontexts problem for hyperreconfigurable architectures. In: Proc. of the International Conference on Field Programmable Logic and Applications (FPL 2004). LNCS, vol. 3205, pp. 251–260 (2004)
Lange, S., Middendorf, M.: Hyperreconfigurable architectures and the partition into hypercontexts problem. J. Parallel Distrib. Comput. 65(6), 743–754 (2005)
Lange, S., Middendorf, M.: Multi task hyperreconfigurable architectures: Models and reconfiguration problems. Int. J. Embed. Syst. 1(3/4), 154–164 (2005)
Lange, S., Middendorf, M.: On the design of two-level reconfigurable architectures. In: Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig05), p. 8 (2005)
Lange, S., Middendorf, M.: Cache architectures for reconfigurable hardware. In: Proc. Int. Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’06), p. 8 (2006)
Lange, S., Middendorf, M.: Granularity aspects for the design of multi-level reconfigurable architectures. In: Proc. IEEE Int. Conf. on Field Prog. Techn. (ICFPT 06), pp. 9–16 (2006)
Lange, S., Middendorf, M.: On multi-level reconfigurable architectures. In: Proc. 13th Reconfigurable Architectures Workshop (RAW 2006), p. 8, IEEE (2006)
Lange, S., Middendorf, M.: Online strategies for the reconfiguration of two-level reconfigurable architectures. In: Proc. Workshop on Dynamically Reconfigurable Systems (DRS) (2007)
Lange, S., Middendorf, M.: Design aspects of multi-level reconfigurable architectures. J. Signal Process. Syst. Signal Image Video Technol. 51(1), 23–37 (2008)
Lange, S., Middendorf, M.: On the reconfiguration costs of models for partially reconfigurable FPGAs. In: Proc. IV Southern Programmable Logic Conference, pp. 111–118 (2008)
Lange, S., Middendorf, M.: Spp1148 booth: Hyperreconfigurable architectures. In: Proc. Int. Conference on Field Programmable Logic and Applications (FPL 2008), p. 353 (2008)
Malik, U.: Configuration encoding techniques for fast fpga reconfiguration. PhD thesis, University of New South Wales (2006)
Pan, J., Mitra, T., Wong, W.F.: Configuration bitstream compression for dynamically reconfigurable FPGAs. In: Proc. of the 2004 IEEE/ACM International conference on Computer-aided design (ICCAD’04), pp. 766–773 (2004)
Sidhu, R., Wadhwa, S., Mai, A., Prasanna, V.: A self-reconfigurable gate array architecture. In: Proc. FPL. LNCS, vol. 1896, pp. 106–120 (2000)
Wadhwa, S., Dandalis, A.: Efficient self-reconfigurable implementations using on-chip memory. In: Proc. FPL. LNCS, vol. 1896, pp. 443–448 (2000)
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Lange, S., Middendorf, M. (2010). Models and Algorithms for Hyperreconfigurable Hardware. In: Platzner, M., Teich, J., Wehn, N. (eds) Dynamically Reconfigurable Systems. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3485-4_4
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DOI: https://doi.org/10.1007/978-90-481-3485-4_4
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