Encapsulating connections on SoC designs using ASM++ charts

Abstract

This article presents a methodology to encapsulate, not only the functionality of several SoC modules, but also the connections between those modules. To achieve these results, the possibilities of Algorithmic State Machines (ASM charts) have been extended to develop a compiler. Using this approach, a SoC design becomes a set of chart boxes and links: several boxes describe parameterized modules in a hierarchical fashion, other boxes encapsulate their connections, and all boxes are linked together using simple lines. At last, a compiler processes all required files and generates the corresponding VHDL or Verilog code, valid for simulation and synthesis. A small SoC design with two DSP processors is shown as an example.