Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort

Abstract

High defect densities in self-assembled nanotechnology require defect tolerant design strategies. This article presents a heuristic that addresses the problem of mapping logic functions onto defective nanocrossbar structures. The heuristic is defect-aware, thus uses a defect map during the logic mapping process. The proposed algorithm involves a two-dimensional sort (2D-Sort) and is significantly faster than the previous works with defect-aware design flow approaches. This is mostly due to the fact that the search space in our case becomes smaller when a 2D-Sort is applied on both the logic function and crossbar tables.