Abstract
This chapter addresses the problem of functional verification of IP cores to be integrated in complex embedded systems. After analyzing the limits of methods based on HDL testbenches or formal verification, a pseudo-random coverage-driven approach is presented (verification environment design guidelines together with a final coverage report summary) and applied to a novel Router IP core design, a key component of Network-on-Chip communication infrastructure in embedded systems.
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Saponara, S., Vitullo, F., Petri, E., Fanucci, L., Coppola, M., Locatelli, R. (2011). Coverage-Driven Verification of HDL IP Cores. In: Conti, M., Orcioni, S., MartÃnez Madrid, N., Seepold, R. (eds) Solutions on Embedded Systems. Lecture Notes in Electrical Engineering, vol 81. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0638-5_8
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DOI: https://doi.org/10.1007/978-94-007-0638-5_8
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