Abstract
MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
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Acknowledgments
This work is supported by the E.C. funded FP7-215244 MOSART Project, www.mosartproject.org
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Candaele, B. et al. (2011). The MOSART Mapping Optimization for Multi-Core ARchiTectures. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_11
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DOI: https://doi.org/10.1007/978-94-007-1488-5_11
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